Abstract: A semiconductor device includes an address input circuit configured to boost a voltage level of at least one bit of a row address to generate a boosting address and to drive a signal of a first node based on other bits of the row address and the boosting address. The semiconductor device also includes a word line selection signal generation circuit configured to drive a signal of a second node based on the signal of the first node and to generate a word line selection signal for selecting a word line based on the signal of the second node.

Abstract: An electronic device includes a target address generation circuit configured to generate a counting signal by counting the number of times each logic level combination of an address is input by performing an internal read operation and an internal write operation during an active operation, configured to store the counting signal as the storage counting signal when the counting signal is counted more than a storage counting signal that is stored therein, and configured to store the address, corresponding to the counting signal, as a target address; and a refresh control circuit configured to control a smart refresh operation on the target address.

Abstract: A memory device includes a memory cell region including a plurality of rows; a row-hammer control circuit including first and second queues, and configured to: read counting data from a row indicated by a row address according to an active command, store the row address in the first queue according to a comparison result of the counting data and a first set value, store the row address in the second queue according to a comparison result of the counting data and a second set value, and select, as a row-hammer address according to a refresh management command or a target refresh command, one of the row addresses stored in the first queue and the second queue; and a row control circuit configured to refresh one or more rows corresponding to the row-hammer address according to the refresh management command or the target refresh command.

Abstract: An electronic device includes a target address generation circuit configured to generate a counting signal by counting the number of times each logic level combination of an address is input by performing an internal read operation and an internal write operation during an active operation, configured to store the counting signal as the storage counting signal when the counting signal is counted more than a storage counting signal that is stored therein, and configured to store the address, corresponding to the counting signal, as a target address; and a refresh control circuit configured to control a smart refresh operation on the target address.

Abstract: A semiconductor device includes an address input circuit configured to boost a voltage level of at least one bit of a row address to generate a boosting address and to drive a signal of a first node based on other bits of the row address and the boosting address. The semiconductor device also includes a word line selection signal generation circuit configured to drive a signal of a second node based on the signal of the first node and to generate a word line selection signal for selecting a word line based on the signal of the second node.

Abstract: An electronic device includes a target address generation circuit configured to generate a counting signal by counting the number of times each logic level combination of an address is input by performing an internal read operation and an internal write operation during an active operation, configured to store the counting signal as the storage counting signal when the counting signal is counted more than a storage counting signal that is stored therein, and configured to store the address, corresponding to the counting signal, as a target address; and a refresh control circuit configured to control a smart refresh operation on the target address.

Abstract: A semiconductor device includes a sense amplification unit suitable for sensing and amplifying data loaded on a data line pair; a pull-up driving unit suitable for supplying a first voltage to a pull-up power line of the sense amplification unit as a pull-up driving voltage in an active mode, and supplying second voltage higher than the first voltage to the pull-up power line as the pull-up driving voltage during an initial period of a precharge mode; a pull-down driving unit suitable for supplying a third voltage to a pull-down power line of the sense amplification unit as a pull-down driving voltage during the active mode and the initial period of the precharge mode; and a post over-driving control unit suitable for adjusting the initial period of the precharge mode by detecting a voltage level of the pull-up power line.

Abstract: A semiconductor device includes a sense amplification unit suitable for sensing and amplifying data loaded on a data line pair; a pull-up driving unit suitable for supplying a first voltage to a pull-up power line of the sense amplification unit as a pull-up driving voltage in an active mode, and supplying second voltage higher than the first voltage to the pull-up power line as the pull-up driving voltage during an initial period of a precharge mode; a pull-down driving unit suitable for supplying a third voltage to a pull-down power line of the sense amplification unit as a pull-down driving voltage during the active mode and the initial period of the precharge mode; and a post over-driving control unit suitable for adjusting the initial period of the precharge mode by detecting a voltage level of the pull-up power line.