Abstract: An electronic device includes a core circuit configured to store write data and a write parity after outputting read data and a read parity in a data masking operation. The electronic device also includes an error correction circuit configured to correct an error included in the read data, based on the read parity; generate the write parity from the error-corrected read data, input data, and masking data; and generate the write data from the error-uncorrected read data, the input data, and the masking data.

Abstract: Disclosed is a neuron circuit in which an overflow signal before fire is retained after the fire. The neuron circuit according to an embodiment of the inventive concept includes a synapse element, a synaptic integration unit and a pulse generation unit. The synapse element receives output signals of a pre-neuron circuit and a post-neuron circuit. The synaptic integration unit includes a capacitor charged by the current flowing into the synapse element depending on the output signals of the pre-neuron circuit and the post-neuron circuit. The pulse generation unit generates an output pulse from the charging voltage of the capacitor.

Abstract: An electronic device includes an operation control circuit and an input data generation circuit. The operation control circuit generates a detection signal and an internal masking signal based on a masking signal and data during a write operation. The input data generation circuit converts input data based on the internal masking signal to generate converted data. In addition, the input data generation circuit selects and outputs either the converted data or drive data as the input data, which are input to a data storage circuit, based on the detection signal.

Abstract: A processing-in-memory (PIM) device includes a multiplication/accumulation (MAC) operator. The MAC operator includes a multiplying block and an adding block. The multiplying block includes a first multiplier and a second multiplier. The first multiplier performs a first multiplying calculation of first half data of first data and first half data of second data. The second multiplier performs a second multiplying calculation of second half data of the first data and second half data of the second data. The adding block performs an adding calculation of first multiplication result data outputted from the first multiplier and second multiplication result data outputted from the second multiplier. The MAC operator receives a test mode signal having a first level to perform a test operation for the multiplying block.

Abstract: The present invention relates to a composition for improvement of female menopausal (climacteric) disorders, comprising as an active ingredient a combination of a red clover extract and a hops extract, more specifically a food composition for improvement of women's menopausal disorders or a pharmaceutical composition for prevention or treatment of women's menopausal disorders, comprising as an active ingredient a combination of a red clover extract and a hops extract; and a method for preparing said composition for improvement of women's menopausal disorders.

Abstract: A processing-in-memory (PIM) device includes a multiplication/accumulation (MAC) operator. The MAC operator includes a multiplying block and an adding block. The multiplying block includes a first multiplier and a second multiplier. The first multiplier performs a first multiplying calculation of first half data of first data and first half data of second data. The second multiplier performs a second multiplying calculation of second half data of the first data and second half data of the second data. The adding block performs an adding calculation of first multiplication result data outputted from the first multiplier and second multiplication result data outputted from the second multiplier. The MAC operator receives a test mode signal having a first level to perform a test operation for the multiplying block.

Abstract: A latch circuit includes a plurality of latch sets, each including an enable latch and a plurality of address latches; and a plurality of latch-width adjusting circuits respectively corresponding to the latch sets, wherein, in each of the plurality of latch sets, the corresponding latch-width adjusting circuit is disposed between the enable latch of the corresponding latch set and the address latch adjacent to the enable latch, and couples the enable latch to the adjacent address latch depending on whether or not the corresponding latch set is used, at an end of a boot-up operation.

Abstract: An electronic device includes an operation control circuit and an input data generation circuit. The operation control circuit generates a detection signal and an internal masking signal based on a masking signal and data during a write operation. The input data generation circuit converts input data based on the internal masking signal to generate converted data. In addition, the input data generation circuit selects and outputs either the converted data or drive data as the input data, which are input to a data storage circuit, based on the detection signal.

Abstract: A method of performing a MAC arithmetic operation includes detecting error correction capability for first data when a command has a logic level combination for performing the MAC arithmetic operation; correcting an error, included in the first data, when the number of erroneous bits included in the first data is equal to or less than the error correction capability; and outputting, to a PIM controller, MAC calculation result data generated by performing the MAC arithmetic operation on the error-corrected first data.

Abstract: A Processing-In-Memory (PIM) device includes an error correction code (ECC) logic circuit and an error accumulation detection circuit. The error correction code (ECC) logic circuit configured to detect an erroneous bits included in first data to generate a parity bit, and to detect an error correction capability of the first data to generate an error correction fail signal. The error accumulation detection circuit configured to generate an error accumulation signal counted by a pulse of the error correction fail signal. The error correction capability set to the maximum number of erroneous bits that can be corrected by performing an ECC operation on the first data.

Abstract: A Processing-In-Memory (PIM) device includes a MAC operator, a first storage region and an error correction code (ECC) logic circuit. The MAC operator performs MAC operation of first data and second data. The first storage region provides the first data to the MAC operator. The error correction code (ECC) logic circuit transmit first encoded data to the first storage region by performing a first ECC encoding operation on the first data. The error correction code (ECC) logic circuit transmit first decoded data generated by performing a first ECC decoding operation of the first encoded data transmitted from the first storage region to the MAC operator. The error correction code (ECC) logic circuit generates an error calculation result signal and transmit the an error calculation result signal to the MAC operator when the number of erroneous bits detected in the first ECC decoding operation exceed an error correction capability.

Abstract: A processing-in-memory (PIM) device includes a multiplication/accumulation (MAC) operator. The MAC operator includes a multiplying block and an adding block. The multiplying block includes a first multiplier and a second multiplier. The first multiplier performs a first multiplying calculation of first half data of first data and first half data of second data. The second multiplier performs a second multiplying calculation of second half data of the first data and second half data of the second data. The adding block performs an adding calculation of first multiplication result data outputted from the first multiplier and second multiplication result data outputted from the second multiplier. The MAC operator receives a test mode signal having a first level to perform a test operation for the multiplying block.

Abstract: A Processing-In-Memory (PIM) device includes a first storage region and a multiplication/accumulation (MAC) calculator. The first storage region configured to store a first data. The MAC operator configured to execute a MAC calculation on the first data and second data in an MAC mode. When an error exists in the first data, the MAC operator compensates multiplication result data generated by a multiplying calculation of the first data and the second data and executes an adding calculation of the compensated multiplication result data.

Abstract: A test method for a memory device which includes performing a first write operation of writing test data to first regions of a normal cell region and a parity cell region, and storing a parity bit generated based on the test data in a temporary storage circuit, performing a second write operation of writing the parity bit stored in the temporary storage circuit to a second region of the parity cell region, performing a first read operation of reading the parity bit from the second region of the parity cell region, and storing the parity bit into the temporary storage circuit, and performing a second read operation of reading the test data from the first regions of the normal cell region and the parity cell region, correcting an error of the test data using the parity bit stored in the temporary storage circuit, and outputting error-corrected test data.

Abstract: Disclosed is a neuron circuit in which an overflow signal before fire is retained after the fire. The neuron circuit according to an embodiment of the inventive concept includes a synapse element, a synaptic integration unit and a pulse generation unit. The synapse element receives output signals of a pre-neuron circuit and a post-neuron circuit. The synaptic integration unit includes a capacitor charged by the current flowing into the synapse element depending on the output signals of the pre-neuron circuit and the post-neuron circuit. The pulse generation unit generates an output pulse from the charging voltage of the capacitor.

Abstract: A memory system may include: a controller suitable for transmitting a command, an address and write data, and receiving read data, the command including a write command, a read command and a masked write command; and a memory device suitable for sequentially performing an internal read operation, an internal modification operation and an internal write operation in response to the masked write command while skipping the internal read operation when the masked write commands for the same address are consecutively inputted after the write command is inputted.

Abstract: A memory system may include: a controller suitable for transmitting a command, an address and write data, and receiving read data, the command including a write command, a read command and a masked write command; and a memory device suitable for sequentially performing an internal read operation, an internal modification operation and an internal write operation in response to the masked write command while skipping the internal read operation when the masked write commands for the same address are consecutively inputted after the write command is inputted.

Abstract: A test method for a memory device may include: performing a first write operation of writing test data to first regions of a normal cell region and a parity cell region, and storing a parity bit generated based on the test data in a temporary storage circuit; performing a second write operation of writing the parity bit stored in the temporary storage circuit to a second region of the parity cell region; performing a first read operation of reading the parity bit from the second region of the parity cell region, and storing the parity bit into the temporary storage circuit; and performing a second read operation of reading the test data from the first regions of the normal cell region and the parity cell region, correcting an error of the test data using the parity bit stored in the temporary storage circuit, and outputting error-corrected test data.

Abstract: A semiconductor memory apparatus includes a first mat, a second mat, a column driver, and a connection circuit. The first mat may include a first mat column line. The second mat may include a second mat column line. The column driver may drive the first mat column line in response to a mat selection signal and a column decoding signal. The connection circuit may electrically couple or separate the second mat column line to or from the first mat column line in response to the mat select signal.

Abstract: A traffic information detection system and method. According to the traffic information detection method of the present invention, at least one loop coil on a road transmits a signal indicative of electric change induced in the loop coil by a vehicle, at least one loop detection device installed at the garden or escape zone of the road receives the signal transmitted from the loop coil and wirelessly transmits a signal indicative of whether or not a vehicle exists on a road, the velocity of and type of the vehicle, and a traffic signal controller wirelessly receives the signal transmitted from the loop detection device, thereby acquiring traffic information.