Patents by Inventor Jeong-Lim Kim

Jeong-Lim Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12170278
    Abstract: A semiconductor device comprising first and second unit cells, the first unit cell comprising a first fin pattern extending in a first direction, a first gate pattern extending in a second direction, and a first contact disposed on a side of the first gate pattern contacting the first fin pattern, the second unit cell comprising a second fin pattern extending in the first direction, a second gate pattern extending in the second direction, and a second contact disposed on a side of the second gate pattern contacting the second fin pattern, wherein the first and second gate patterns are spaced apart and lie on a first straight line extending in the second direction, the first and second contacts are spaced apart and lie on a second straight line extending in the second direction, and a first middle contact is disposed on and connects the first and second contacts.
    Type: Grant
    Filed: December 14, 2022
    Date of Patent: December 17, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeong-Lim Kim, Myung Soo Noh, No Young Chung, Seok Yun Jeong, Young Han Kim
  • Publication number: 20230109875
    Abstract: A semiconductor device comprising first and second unit cells, the first unit cell comprising a first fin pattern extending in a first direction, a first gate pattern extending in a second direction, and a first contact disposed on a side of the first gate pattern contacting the first fin pattern, the second unit cell comprising a second fin pattern extending in the first direction, a second gate pattern extending in the second direction, and a second contact disposed on a side of the second gate pattern contacting the second fin pattern, wherein the first and second gate patterns are spaced apart and lie on a first straight line extending in the second direction, the first and second contacts are spaced apart and lie on a second straight line extending in the second direction, and a first middle contact is disposed on and connects the first and second contacts.
    Type: Application
    Filed: December 14, 2022
    Publication date: April 13, 2023
    Inventors: Jeong-Lim KIM, Myung Soo NOH, No Young CHUNG, Seok Yun JEONG, Young Han KIM
  • Publication number: 20230041075
    Abstract: An optical proximity correction method includes designing a mask design. The designing of the mask design includes setting a reference point of the mask design, calculating a plurality of chief ray angles of a plurality of points of interest on the mask design, respectively, each of the plurality of points of interest having a corresponding distance from the reference point, finding, among the plurality of points of interest, a first point of interest having a maximum chief ray angle among the plurality of chief ray angles, a distance of the first point of interest from the reference point being set as a deteriorated distance, and compensating for distortion of an image to be transferred from a pattern located at the deteriorated distance from the reference point of the mask design.
    Type: Application
    Filed: February 14, 2022
    Publication date: February 9, 2023
    Inventors: Jeong-Lim KIM, Jae Myoung LEE, Sung Gon JUNG
  • Patent number: 11557582
    Abstract: A semiconductor device comprising first and second unit cells, the first unit cell comprising a first fin pattern extending in a first direction, a first gate pattern extending in a second direction, and a first contact disposed on a side of the first gate pattern contacting the first fin pattern, the second unit cell comprising a second fin pattern extending in the first direction, a second gate pattern extending in the second direction, and a second contact disposed on a side of the second gate pattern contacting the second fin pattern, wherein the first and second gate patterns are spaced apart and lie on a first straight line extending in the second direction, the first and second contacts are spaced apart and lie on a second straight line extending in the second direction, and a first middle contact is disposed on and connects the first and second contacts.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: January 17, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeong-Lim Kim, Myung Soo Noh, No Young Chung, Seok Yun Jeong, Young Han Kim
  • Patent number: 10991692
    Abstract: A semiconductor device comprises a first fin-type pattern comprising a first long side extending in a first direction, and a first short side extending in a second direction. A second fin-type pattern is arranged substantially parallel to the first fin-type pattern. A first gate electrode intersects the first fin-type pattern and the second fin-type pattern. The second fin-type pattern comprises a protrusion portion that protrudes beyond the first short side of the first fin-type pattern. The first gate electrode overlaps with an end portion of the first fin-type pattern that comprises the first short side of the first fin-type pattern. At least part of a first sidewall of the first fin-type pattern that defines the first short side of the first fin-type pattern is defined by a first trench having a first depth. The first trench directly adjoins a second trench having a second, greater, depth.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: April 27, 2021
    Inventors: Myoung Ho Kang, Gyeongseop Kim, Jeong Lim Kim, Jae Myoung Lee, Heung Suk Oh, Yeon Hwa Lim, Joong Won Jeon, Sung Min Kim
  • Publication number: 20210066283
    Abstract: A semiconductor device comprising first and second unit cells, the first unit cell comprising a first fin pattern extending in a first direction, a first gate pattern extending in a second direction, and a first contact disposed on a side of the first gate pattern contacting the first fin pattern, the second unit cell comprising a second fin pattern extending in the first direction, a second gate pattern extending in the second direction, and a second contact disposed on a side of the second gate pattern contacting the second fin pattern, wherein the first and second gate patterns are spaced apart and lie on a first straight line extending in the second direction, the first and second contacts are spaced apart and lie on a second straight line extending in the second direction, and a first middle contact is disposed on and connects the first and second contacts.
    Type: Application
    Filed: April 1, 2020
    Publication date: March 4, 2021
    Inventors: Jeong-Lim KIM, Myung Soo NOH, No Young CHUNG, Seok Yun JEONG, Young Han KIM
  • Publication number: 20200235097
    Abstract: A semiconductor device comprises a first fin-type pattern comprising a first long side extending in a first direction, and a first short side extending in a second direction. A second fin-type pattern is arranged substantially parallel to the first fin-type pattern. A first gate electrode intersects the first fin-type pattern and the second fin-type pattern. The second fin-type pattern comprises a protrusion portion that protrudes beyond the first short side of the first fin-type pattern. The first gate electrode overlaps with an end portion of the first fin-type pattern that comprises the first short side of the first fin-type pattern. At least part of a first sidewall of the first fin-type pattern that defines the first short side of the first fin-type pattern is defined by a first trench having a first depth. The first trench directly adjoins a second trench having a second, greater, depth.
    Type: Application
    Filed: April 6, 2020
    Publication date: July 23, 2020
    Inventors: Myoung Ho Kang, Gyeongseop Kim, Jeong Lim Kim, Jae Myoung Lee, Heung Suk Oh, Yeon Hwa Lim, Joong Won Jeon, Sung Min Kim
  • Patent number: 10643998
    Abstract: A semiconductor device comprises a first fin-type pattern comprising a first long side extending in a first direction, and a first short side extending in a second direction. A second fin-type pattern is arranged substantially parallel to the first fin-type pattern. A first gate electrode intersects the first fin-type pattern and the second fin-type pattern. The second fin-type pattern comprises a protrusion portion that protrudes beyond the first short side of the first fin-type pattern. The first gate electrode overlaps with an end portion of the first fin-type pattern that comprises the first short side of the first fin-type pattern. At least part of a first sidewall of the first fin-type pattern that defines the first short side of the first fin-type pattern is defined by a first trench having a first depth. The first trench directly adjoins a second trench having a second, greater, depth.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: May 5, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myoung Ho Kang, Gyeongseop Kim, Jeong Lim Kim, Jae Myoung Lee, Heung Suk Oh, Yeon Hwa Lim, Joong Won Jeon, Sung Min Kim
  • Publication number: 20200043922
    Abstract: A semiconductor device comprises a first fin-type pattern comprising a first long side extending in a first direction, and a first short side extending in a second direction. A second fin-type pattern is arranged substantially parallel to the first fin-type pattern. A first gate electrode intersects the first fin-type pattern and the second fin-type pattern. The second fin-type pattern comprises a protrusion portion that protrudes beyond the first short side of the first fin-type pattern. The first gate electrode overlaps with an end portion of the first fin-type pattern that comprises the first short side of the first fin-type pattern. At least part of a first sidewall of the first fin-type pattern that defines the first short side of the first fin-type pattern is defined by a first trench having a first depth. The first trench directly adjoins a second trench having a second, greater, depth.
    Type: Application
    Filed: October 4, 2019
    Publication date: February 6, 2020
    Inventors: Myoung Ho Kang, Gyeongseop Kim, Jeong Lim Kim, Jae Myoung Lee, Heung Suk Oh, Yeon Hwa Lim, Joong Won Jeon, Sung Min Kim
  • Patent number: 10475789
    Abstract: A semiconductor device comprises a first fin-type pattern comprising a first long side extending in a first direction, and a first short side extending in a second direction. A second fin-type pattern is arranged substantially parallel to the first fin-type pattern. A first gate electrode intersects the first fin-type pattern and the second fin-type pattern. The second fin-type pattern comprises a protrusion portion that protrudes beyond the first short side of the first fin-type pattern. The first gate electrode overlaps with an end portion of the first fin-type pattern that comprises the first short side of the first fin-type pattern. At least part of a first sidewall of the first fin-type pattern that defines the first short side of the first fin-type pattern is defined by a first trench having a first depth. The first trench directly adjoins a second trench having a second, greater, depth.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: November 12, 2019
    Assignee: Samsung Electroncis Co., Ltd.
    Inventors: Myoung Ho Kang, Gyeongseop Kim, Jeong Lim Kim, Jae Myoung Lee, Heung Suk Oh, Yeon Hwa Lim, Joong Won Jeon, Sung Min Kim
  • Patent number: 10409169
    Abstract: Methods of inspecting photomasks are provided. A method of inspecting a photomask includes electronically inspecting a first mask pattern in a mask region of the photomask and refraining from electronically inspecting a separate second mask pattern in the mask region of the photomask. The first mask pattern includes a geometric feature that corresponds to at least a portion of the second mask pattern. Moreover, the mask region is outside of a scribe lane region of the photomask. Related methods of manufacturing photomasks and methods of manufacturing semiconductor devices are also provided.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: September 10, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeong-Lim Kim, Jong-Doo Kim, Joong-Won Jeon
  • Publication number: 20180286859
    Abstract: A semiconductor device comprises a first fin-type pattern comprising a first long side extending in a first direction, and a first short side extending in a second direction. A second fin-type pattern is arranged substantially parallel to the first fin-type pattern. A first gate electrode intersects the first fin-type pattern and the second fin-type pattern. The second fin-type pattern comprises a protrusion portion that protrudes beyond the first short side of the first fin-type pattern. The first gate electrode overlaps with an end portion of the first fin-type pattern that comprises the first short side of the first fin-type pattern. At least part of a first sidewall of the first fin-type pattern that defines the first short side of the first fin-type pattern is defined by a first trench having a first depth. The first trench directly adjoins a second trench having a second, greater, depth.
    Type: Application
    Filed: December 11, 2017
    Publication date: October 4, 2018
    Inventors: Myoung Ho Kang, Gyeongseop Kim, Jeong Lim Kim, Jae Myoung Lee, Heung Suk Oh, Yeon Hwa Lim, Joong Won Jeon
  • Publication number: 20170371250
    Abstract: Methods of inspecting photomasks are provided. A method of inspecting a photomask includes electronically inspecting a first mask pattern in a mask region of the photomask and refraining from electronically inspecting a separate second mask pattern in the mask region of the photomask. The first mask pattern includes a geometric feature that corresponds to at least a portion of the second mask pattern. Moreover, the mask region is outside of a scribe lane region of the photomask. Related methods of manufacturing photomasks and methods of manufacturing semiconductor devices are also provided.
    Type: Application
    Filed: April 6, 2017
    Publication date: December 28, 2017
    Inventors: Jeong-Lim KIM, Jong-Doo KIM, Joong-Won JEON
  • Publication number: 20070173049
    Abstract: There is provided a capacitor and a method for fabricating the same. The method may include forming an interlayer insulation layer on a semiconductor substrate, patterning the interlayer insulation layer to form a contact hole exposing a region of the semiconductor substrate and forming a contact plug by filling the contact hole, wherein a top of the contact plug may have a height identical to that of the interlayer insulation layer. The method may further include forming a recess on the interlayer insulation layer, the recess exposing a portion of the contact plug, forming a bottom electrode on an inner profile of the recess including sides of the contact plug and depositing a dielectric layer and a top electrode on a profile of the semiconductor substrate including the bottom electrode to form a capacitor.
    Type: Application
    Filed: December 6, 2006
    Publication date: July 26, 2007
    Inventors: Jeong-Lim Kim, Kwan-Young Youn