Patents by Inventor Jeong-no Lee

Jeong-no Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060006417
    Abstract: The invention provides an electronic device configured to prevent or reduce electrostatic discharge from causing a pixel to malfunction. An electronic device manufactured according to the principles of the invention may include multiple conductive layers that cross but do not contact each other, wherein at least one of the conductive layers includes a width change part having a width that changes in a length direction of the at least one of the conductive layers, and a tab connected to at least one of the conductive layers at a region thereof that does not cross a neighboring conductive layer. Alternatively, the width change part may have a width that continuously varies along a length of the at least one conductive layer and may also have obtuse corner edges. The invention also provides a flat organic electroluminescent display (OELD) or LCD display device that includes such an electronic device.
    Type: Application
    Filed: June 30, 2005
    Publication date: January 12, 2006
    Inventors: Eun-Ah Kim, Jeong-No Lee, Su-Mi Lee, Bong-Ju Shin, Mi-Jin Lee
  • Publication number: 20050062408
    Abstract: An active matrix organic light emitting device having a structure where a plurality of emission layers having each separate current path are stacked. In the active matrix organic light emitting device of the present invention, a plurality of emission layers are stacked on an insulating substrate. A thin film transistor is formed on the insulating substrate and is connected in common with a number of electrode layers to independently drive the plurality of emission layers.
    Type: Application
    Filed: September 1, 2004
    Publication date: March 24, 2005
    Inventors: Jeong-Geun Yoo, Jeong-No Lee
  • Patent number: 6528361
    Abstract: The present invention relates to a process for preparing a polycrystalline silicon thin film comprising a step of microwave annealing and crystallization of an amorphous thin film of silicon semiconductor, silicon semiconductor added with impurities, IV family semiconductor comprising Si alloy such as Si1−xGex, III-V family and II-VI family semiconductor. The process for preparing polycrystalline silicon thin film of the present invention comprises the steps of: immersing a washed substrate into a deposition equipment and heating the substrate; depositing an amorphous or microcrystalline silicon thin film on the substrate; and, annealing the deposited thin film employing microwave for crystallization.
    Type: Grant
    Filed: August 14, 2000
    Date of Patent: March 4, 2003
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Byung-Tae Ahn, Do-Kyung Kim, Jong-Hee Kim, Jeong-No Lee, Yoon-Chang Kim
  • Patent number: 6451630
    Abstract: A method for manufacturing a thin film transistor is disclosed. Afterforming a channel region on a surface of a substrate, an insulating layer is deposited on the surface of the substrate to cover the channel region. The insulating layer is pataterned such that a portion of the channel region is exposed. Then, a silicon layer and a metal layer are sequentially deposited on the insulating layer. The silicon and metal layers are etched to define source, drain and gate electrode sections. After doping positive ions on a portion corresponding to a MOS circuit portion, an intermediate insulating layer is deposited on the metal layer while covering the source, drain and gate electrode sections. The intermediate insulating layer is patterned to form a plurality of contact holes. An electrode material is deposited on the intermediate insulating layer and patterned to define a pixel electrode section and a wire section.
    Type: Grant
    Filed: December 8, 2000
    Date of Patent: September 17, 2002
    Assignee: Samsung SDI Co., Ltd.
    Inventor: Jeong-no Lee
  • Publication number: 20010003657
    Abstract: A method for manufacturing a thin film transistor is disclosed. Afterforming a channel region on a surface of a substrate, an insulating layer is deposited on the surface of the substrate to cover the channel region. The insulating layer is pataterned such that a portion of the channel region is exposed. Then, a silicon layer and a metal layer are sequentially deposited on the insulating layer. The silicon and metal layers are etched to define source, drain and gate electrode sections. After doping positive ions on a portion corresponding to a MOS circuit portion, an intermediate insulating layer is deposited on the metal layer while covering the source, drain and gate electrode sections. The intermediate insulating layer is patterned to form a plurality of contact holes. An electrode material is deposited on the intermediate insulating layer and patterned to define a pixel electrode section and a wire section.
    Type: Application
    Filed: December 8, 2000
    Publication date: June 14, 2001
    Applicant: Samsung SDI Co., Ltd.
    Inventor: Jeong-No Lee