Abstract: Embodiments of the invention provide a method for fabricating a system in package. In one embodiment, the method comprises preparing a printed circuit board (PCB) strip comprising a plurality of individual PCBs, stacking a plurality of first semiconductor chips and forming an encapsulant on a first surface of a first individual PCB of the plurality of individual PCBs to form a first semiconductor chip stack structure comprising a first semiconductor chip stack, and performing a first test adapted to test one of the first semiconductor chips in the first semiconductor chip stack. The method further comprises flip chip bonding a second semiconductor chip to a second surface of the first individual PCB if the first semiconductor chip stack structure meets a test standard based on a result of the first test, and dividing the first semiconductor chip stack structure to form a system in package.

Abstract: A chip stack structure having a shielding capability may comprise a wiring substrate, the wiring substrate including a ground layer. The structure may also comprise a first chip attached on an upper surface of the wiring substrate and electrically connected to the ground layer. The structure may also comprise a plurality of first bonding wires which electrically connect the first chip to the wiring substrate. The structure may also comprise a shield plate attached to the first chip and detached from at least one of the plurality of first bonding wires, the shield plate being configured to cover the first chip and at least one of the plurality of first bonding wires. The structure may also comprise a grounding wire which connects the shield plate to the ground layer of the wiring substrate. The structure may also comprise a second chip attached to and supported by the shield plate.

Abstract: Embodiments of the invention provide a method for fabricating a system in package. In one embodiment, the method comprises preparing a printed circuit board (PCB) strip comprising a plurality of individual PCBs, stacking a plurality of first semiconductor chips and forming an encapsulant on a first surface of a first individual PCB of the plurality of individual PCBs to form a first semiconductor chip stack structure comprising a first semiconductor chip stack, and performing a first test adapted to test one of the first semiconductor chips in the first semiconductor chip stack. The method further comprises flip chip bonding a second semiconductor chip to a second surface of the first individual PCB if the first semiconductor chip stack structure meets a test standard based on a result of the first test, and dividing the first semiconductor chip stack structure to form a system in package.

Abstract: Disclosed is a semiconductor device packaging technique that is capable of resolving a problem of instability of bonding wires when stacking a plurality of semiconductor chips. The technique is also capable of realizing a slim, light and small package. The semiconductor device package includes a substrate having a substrate pad on a surface thereof, one or more memory chips stacked on the substrate with each memory chip having a pad connected to a common pin receiving a common signal applied to all the memory chips, an interposer chip stacked on the substrate and having an interconnection wire connected to the memory chip pad, the common pin of each of the memory chips being electrically connected to the interconnection wire via the memory chip pad, and a logic chip stacked on the substrate and having a bypass circuit which electrically connects or disconnects the interconnection wire to or from the substrate pad.

Abstract: Embodiments of the invention provide a method for fabricating a system in package. In one embodiment, the method comprises preparing a printed circuit board (PCB) strip comprising a plurality of individual PCBs, stacking a plurality of first semiconductor chips and forming an encapsulant on a first surface of a first individual PCB of the plurality of individual PCBs to form a first semiconductor chip stack structure comprising a first semiconductor chip stack, and performing a first test adapted to test one of the first semiconductor chips in the first semiconductor chip stack. The method further comprises flip chip bonding a second semiconductor chip to a second surface of the first individual PCB if the first semiconductor chip stack structure meets a test standard based on a result of the first test, and dividing the first semiconductor chip stack structure to form a system in package.

Abstract: A stacked semiconductor package can be formed according to principles of the present invention by stacking a plurality of semiconductor packages. A method of manufacturing the stacked semiconductor packages provides a simple manufacturing process. The stacked semiconductor package embodying these principles preferably includes a base substrate, one or more lower semiconductor packages, one or more upper semiconductor packages, and an external sealing agent. Each lower semiconductor package can include a first inner substrate, one or more first semiconductor chips electrically connected to and mounted on the first inner substrate, a first inner sealing agent sealing the first semiconductor chips, and a first contact portion. Each lower semiconductor package is preferably mounted on a portion of an upper surface of the base substrate and is electrically connected to the base substrate via the first contact portion.

Abstract: Embodiments of the invention provide a method for fabricating a system in package. In one embodiment, the method comprises preparing a printed circuit board (PCB) strip comprising a plurality of individual PCBs, stacking a plurality of first semiconductor chips and forming an encapsulant on a first surface of a first individual PCB of the plurality of individual PCBs to form a first semiconductor chip stack structure comprising a first semiconductor chip stack, and performing a first test adapted to test one of the first semiconductor chips in the first semiconductor chip stack. The method further comprises flip chip bonding a second semiconductor chip to a second surface of the first individual PCB if the first semiconductor chip stack structure meets a test standard based on a result of the first test, and dividing the first semiconductor chip stack structure to form a system in package.

Abstract: A chip stack structure having a shielding capability may comprise a wiring substrate, the wiring substrate including a ground layer. The structure may also comprise a first chip attached on an upper surface of the wiring substrate and electrically connected to the ground layer. The structure may also comprise a plurality of first bonding wires which electrically connect the first chip to the wiring substrate. The structure may also comprise a shield plate attached to the first chip and detached from at least one of the plurality of first bonding wires, the shield plate being configured to cover the first chip and at least one of the plurality of first bonding wires. The structure may also comprise a grounding wire which connects the shield plate to the ground layer of the wiring substrate. The structure may also comprise a second chip attached to and supported by the shield plate.

Abstract: Disclosed is a semiconductor device packaging technique that is capable of resolving a problem of instability of bonding wires when stacking a plurality of semiconductor chips. The technique is also capable of realizing a slim, light and small package. The semiconductor device package includes a substrate having a substrate pad on a surface thereof, one or more memory chips stacked on the substrate with each memory chip having a pad connected to a common pin receiving a common signal applied to all the memory chips, an interposer chip stacked on the substrate and having an interconnection wire connected to the memory chip pad, the common pin of each of the memory chips being electrically connected to the interconnection wire via the memory chip pad, and a logic chip stacked on the substrate and having a bypass circuit which electrically connects or disconnects the interconnection wire to or from the substrate pad.

Abstract: A multi-chip package includes a substrate having first and second substrate pads, ball pads electrically connected to the first and second substrate pads, a first chip attached on the substrate and having first chip pads flip-chip bonded to the first substrate pads, and a second chip attached on the first chip and having second chip pads wire-bonded to the second substrate pads. The second chip may have overhang portions. Solder balls may be formed on the ball pads and act as external connection terminals. A support member may be interposed between the first chip and the second chip to support the overhang portions of the second chip.