Patents by Inventor Jeong-Ok Cha

Jeong-Ok Cha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods of forming wiring structures including a plurality of metal layers
    Patent number: 9773699
    Abstract: In a method of forming a wiring structure, a lower structure is formed on a substrate. An insulating interlayer is formed on the lower structure. The insulating interlayer is partially removed to form at least one via hole and a dummy via hole. An upper portion of the insulating interlayer is partially removed to form a trench connecting the via hole and the dummy via hole. A first metal layer filling the via hole and the dummy via hole is formed. A second metal layer filling the trench is formed on the first metal layer.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: September 26, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Jin Lee, Rak-Hwan Kim, Byung-Hee Kim, Jin-Nam Kim, Tsukasa Matsuda, Wan-Soo Park, Nae-In Lee, Jae-Won Chang, Eun-Ji Jung, Jeong-Ok Cha, Jae-Won Hwang, Jung-Ha Hwang
  • METHODS OF FORMING WIRING STRUCTURES
    Publication number: 20160293484
    Abstract: In a method of forming a wiring structure, a lower structure is formed on a substrate. An insulating interlayer is formed on the lower structure. The insulating interlayer is partially removed to form at least one via hole and a dummy via hole. An upper portion of the insulating interlayer is partially removed to form a trench connecting the via hole and the dummy via hole. A first metal layer filling the via hole and the dummy via hole is formed. A second metal layer filling the trench is formed on the first metal layer.
    Type: Application
    Filed: January 19, 2016
    Publication date: October 6, 2016
    Inventors: Jong-Jin Lee, Rak-Hwan Kim, Byung-Hee Kim, Jin-Nam Kim, Tsukasa Matsuda, Wan-Soo Park, Nae-In Lee, Jae-Won Chang, Eun-Ji Jung, Jeong-Ok Cha, Jae-Won Hwang, Jung-Ha Hwang
  • METHODS OF FORMING WIRING STRUCTURES IN A SEMICONDUCTOR DEVICE
    Publication number: 20160276267
    Abstract: Methods of forming wiring structures and methods of manufacturing semiconductor devices include forming a lower structure on a substrate, forming an interlayer insulating film including an opening on the lower structure, forming a liner film on an inner surface of the opening, treating a surface of the liner film by an ion bombardment, and forming a first conductive film on the liner film. The first conductive film is formed to be at least partially filled in the opening through a reflow process. Related wiring structures and semiconductor devices are also discussed.
    Type: Application
    Filed: February 8, 2016
    Publication date: September 22, 2016
    Inventors: Jong-Jin Lee, Rak-Hwan Kim, Byung-Hee Kim, Jin-Nam Kim, Tsukasa Matsuda, Nae-In Lee, Jeong-Ok Cha, Jung-Ha Hwang