Patents by Inventor Jeong Rae Ro

Jeong Rae Ro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230369826
    Abstract: A vertical-cavity surface-emitting laser (VCSEL) including a substrate including a plurality of emitters forming an array region, a lower mirror, an upper mirror, an active layer interposed between the lower mirror and the upper mirror, an aperture forming layer interposed between the upper mirror and the active layer and including an oxidation region and a window region, a connector disposed on the upper mirror, a plurality of oxidation holes passing through the upper mirror and the aperture forming layer, an upper insulation layer covering the plurality of oxidation holes, and a pad electrically connected to the connector, in which at least a portion of the connector is disposed in the plurality of oxidation holes, and the plurality of emitters is disposed in substantially a honeycomb shape on the substrate.
    Type: Application
    Filed: July 24, 2023
    Publication date: November 16, 2023
    Inventors: Ki Hwang LEE, Jeong Rae RO, Byueng Su YOO, Yoon Sang JEON, Gong Hee CHOI
  • Patent number: 11764545
    Abstract: A vertical-cavity surface-emitting laser (VCSEL) including a substrate including a plurality of emitters forming an array region, a lower mirror, an upper mirror, an active layer interposed between the lower mirror and the upper mirror, an aperture forming layer interposed between the upper mirror and the active layer and including an oxidation region and a window region, a connector disposed on the upper mirror, a plurality of oxidation holes passing through the upper mirror and the aperture forming layer, an upper insulation layer covering the plurality of oxidation holes, and a pad electrically connected to the connector, in which at least a portion of the connector is disposed in the plurality of oxidation holes, the plurality of emitters is disposed in substantially a honeycomb shape on the substrate, and the pad is formed on one side of the substrate adjacent to the array region.
    Type: Grant
    Filed: July 31, 2022
    Date of Patent: September 19, 2023
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Ki Hwang Lee, Jeong Rae Ro, Byueng Su Yoo, Yoon Sang Jeon, Gong Hee Choi
  • Patent number: 11764544
    Abstract: A vertical-cavity surface-emitting laser (VCSEL) including a lower mirror, an upper mirror, an active layer interposed between the lower mirror and the upper mirror, an aperture forming layer interposed between the upper mirror and the active layer, and including an oxidation layer and a window layer surrounded by the oxidation layer, a ring-shaped trench passing through the upper mirror, the aperture forming layer, and the active layer to define an isolation region therein, and a plurality of oxidation holes disposed in the isolation region surrounded by the trench, and passing through the upper mirror and the aperture forming layer.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: September 19, 2023
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Ki Hwang Lee, Byueng Su Yoo, Jeong Rae Ro
  • Publication number: 20220368106
    Abstract: A vertical-cavity surface-emitting laser (VCSEL) including a substrate including a plurality of emitters forming an array region, a lower mirror, an upper mirror, an active layer interposed between the lower mirror and the upper mirror, an aperture forming layer interposed between the upper mirror and the active layer and including an oxidation region and a window region, a connector disposed on the upper mirror, a plurality of oxidation holes passing through the upper mirror and the aperture forming layer, an upper insulation layer covering the plurality of oxidation holes, and a pad electrically connected to the connector, in which at least a portion of the connector is disposed in the plurality of oxidation holes, the plurality of emitters is disposed in substantially a honeycomb shape on the substrate, and the pad is formed on one side of the substrate adjacent to the array region.
    Type: Application
    Filed: July 31, 2022
    Publication date: November 17, 2022
    Inventors: Ki Hwang LEE, Jeong Rae Ro, Byueng Su Yoo, Yoon Sang Jeon, Gong Hee Choi
  • Patent number: 11404848
    Abstract: A vertical-cavity surface-emitting laser (VCSEL) including a lower mirror, an upper mirror having an insulation region including implanted ions and an isolation region surrounded by the insulation region, an active layer interposed between the lower mirror and the upper mirror, an aperture forming layer interposed between the upper mirror and the active layer, and including an oxidation layer and a window layer surrounded by the oxidation layer, and a plurality of oxidation holes disposed in the isolation region and passing through the upper mirror and the aperture forming layer.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: August 2, 2022
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Ki Hwang Lee, Jeong Rae Ro, Byueng Su Yoo, Yoon Sang Jeon, Gong Hee Choi
  • Publication number: 20200280175
    Abstract: A vertical-cavity surface-emitting laser (VCSEL) including a lower mirror, an upper mirror, an active layer interposed between the lower mirror and the upper mirror, an aperture forming layer interposed between the upper mirror and the active layer, and including an oxidation layer and a window layer surrounded by the oxidation layer, a ring-shaped trench passing through the upper mirror, the aperture forming layer, and the active layer to define an isolation region therein, and a plurality of oxidation holes disposed in the isolation region surrounded by the trench, and passing through the upper mirror and the aperture forming layer.
    Type: Application
    Filed: February 21, 2020
    Publication date: September 3, 2020
    Inventors: Ki Hwang LEE, Byueng Su YOO, Jeong Rae RO
  • Publication number: 20200203927
    Abstract: A vertical-cavity surface-emitting laser (VCSEL) including a lower mirror, an upper mirror having an insulation region including implanted ions and an isolation region surrounded by the insulation region, an active layer interposed between the lower mirror and the upper mirror, an aperture forming layer interposed between the upper mirror and the active layer, and including an oxidation layer and a window layer surrounded by the oxidation layer, and a plurality of oxidation holes disposed in the isolation region and passing through the upper mirror and the aperture forming layer.
    Type: Application
    Filed: December 19, 2019
    Publication date: June 25, 2020
    Inventors: Ki Hwang Lee, Jeong Rae Ro, Byueng Su Yoo, Yoon Sang Jeon, Gong Hee Choi
  • Patent number: 6242275
    Abstract: A method for manufacturing quantum wires is provided in which a stacked structure having AlAs layers and GaAs layers alternatively is formed, V-grooves are formed beside the GaAs layers and the quantum wires are formed using the V-grooves.
    Type: Grant
    Filed: August 21, 1998
    Date of Patent: June 5, 2001
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sung Bock Kim, Jeong Rae Ro, El Hang Lee
  • Patent number: 6074936
    Abstract: A method of fabricating quantum wire structures and devices, and quantum dot structures and devices comprise steps of: depositing an insulating layer on a semiconductor substrate, forming a line patterns and a square patterns in an insulating layer, forming a V-grooved patterned structures and a reverse quadrilateral pyramid patterned structures by thermal etching to evaporate portions of the quantum well layer that are not protected by line-shaped mask regions and square-shaped mask regions of the masking layer, forming a quantum wires and a quantum dots by alternatively growing a barrier layer and an active layer on a V-grooved patterned substrate and a reverse quadrilateral pyramid patterned substrate.
    Type: Grant
    Filed: June 8, 1998
    Date of Patent: June 13, 2000
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jeong Rae Ro, Sung Bock Kim, El Hang Lee
  • Patent number: 6033972
    Abstract: The formation of self-assembled GaAs quantum dots on (100) GaAs via chemical beam epitaxy (CBE) technique using triethylgallium (TEGa) and arsine (AsH.sub.3) is disclosed. GaAs quantum dots are easy to grow from Ga-droplets which are successively supplied with arsine with neither pattern definition nor pre-treatment steps prior to the growth. The density and the size of Ga-droplets are found to be sensitive to the growth conditions, such as the growth temperature, the beam equivalent pressure of TEGa, and the amount of TEGa supplied. This invention suggests that, unlike Stranski-Krastanow growth, the Ga-droplet-induced CBE technique can be a useful method for the fabrication of quantum dot structure by simple change of gas supply mode, even in lattice-matched system.
    Type: Grant
    Filed: August 17, 1998
    Date of Patent: March 7, 2000
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jeong Rae Ro, Sung Bock Kim, El Hang Lee
  • Patent number: 5858818
    Abstract: An epitaxial growth method for a compound semiconductor thin film, capable of forming a p-n junction with an atomic-scale ultra-micro structure is disclosed. The method involves loading the compound semiconductor substrate in a reaction chamber, injecting Group V and III metal organic source gases not processed by a thermal pre-decomposition process into the reaction chamber, and growing a p- or n-type compound semiconductor on the compound semiconductor substrate while adjusting the growth temperature of the p- or n-type compound semiconductor.
    Type: Grant
    Filed: September 16, 1996
    Date of Patent: January 12, 1999
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jeong-Rae Ro, Seong-Bock Kim, El-Hang Lee
  • Patent number: 5833870
    Abstract: A method for forming a highly dense quantum wire, the method comprising the steps of: depositing a dielectric mask having dielectric patterns on the top surface of a semiconductor (100) substrate; forming the dielectric patterns in parallel to a (011) orientation on the semiconductor substrate; exposing a (111)B side and a(111)B side by chemical etching a selected region between the patterns so that the semiconductor substrate has a dove-tail shape; forming a buffer layer on the dove-tail semiconductor substrate; forming the first barrier layer on the buffer layer; forming a well layer on the first barrier layer; and forming the second barrier layer on the well layer.
    Type: Grant
    Filed: April 3, 1997
    Date of Patent: November 10, 1998
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sung Bock Kim, Jeong Rae Ro, El Hang Lee
  • Patent number: 5824453
    Abstract: Disclosed is a fabricating method of a GaAs substrate having a V-shaped groove in a higher density, that is a double density, the method comprising the steps of forming a Si.sub.3 N.sub.4 layer on a main surface of the GaAs substrate; patterning the Si.sub.3 N.sub.4 layer using a photo-lithography to form a patterned Si.sub.3 N.sub.4 layer having a minimum width; wet-etching the GaAs substrate using the patterned Si.sub.3 N.sub.4 layer as a mask, so as to form (111) and (100) surfaces of the GaAs substrate beneath the patterned Si.sub.3 N.sub.4 ; selectively growing a GaAs film on the GaAs substrate etched thus using the patterned Si.sub.3 N.sub.4 layer as a mask so as to form the GaAs film with two (111) facets only on a (100) surface of the GaAs substrate; and removing the Si.sub.3 N.sub.4 layer. The V-shaped grooves can be formed on a GaAs substrate utilizing a difference of growth rate caused by surface orientation of the substrate, and therefore the grooves can be formed in double density.
    Type: Grant
    Filed: October 9, 1997
    Date of Patent: October 20, 1998
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sung-Bock Kim, Seong-Ju Park, Jeong-Rae Ro, El-Hang Lee
  • Patent number: 5770475
    Abstract: A crystal growth method for a compound semiconductor is capable of forming a plurality of quantum wells (formed of a barrier layer having a large energy band gap and an active layer having a small energy band gap) on the compound semiconductor substrate. After etching a V-shaped groove having a (111) surface with a predetermined angle .theta.1 with respect to the (100) surface on the GaAs semiconductor substrate, the substrate is further etched by a hydrochloric solution and a solution of H.sub.2 SO.sub.4 :H.sub.2 O.sub.2 :H.sub.2 O=20:1 to cause the V-shaped groove walls to become a non-(111) surface having a lower predetermined slope angle .theta.2. The quantum wells then grown in the bottom of the V-shaped groove will be effectively disconnected from simultaneous growths on the side walls of the groove thus giving rise to closely controlled multi-dimensional quantum well structures.
    Type: Grant
    Filed: September 23, 1996
    Date of Patent: June 23, 1998
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sung-Bock Kim, Jeong-Rae Ro, El-Hang Lee