Patents by Inventor Jeong Sang KANG

Jeong Sang KANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230032560
    Abstract: Provided herein may be a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device may include a dummy stacked body including a plurality of first material layers and second material layers alternately stacked in a contact area, at least one contact plug formed to vertically pass through a portion or an entirety of the dummy stacked body, and a capacitor comprising a first electrode body and a second electrode body, the first and second electrode bodies formed around the at least one contact plug and vertically passed through a portion or an entirety of the dummy stacked body.
    Type: Application
    Filed: December 9, 2021
    Publication date: February 2, 2023
    Applicant: SK hynix Inc.
    Inventor: Jeong Sang KANG
  • Patent number: 10396168
    Abstract: There are provided a semiconductor device and a manufacturing method thereof. The semiconductor device includes a pipe gate stack structure in which a portion of a first channel layer is buried. The semiconductor device includes the pipe gate stack structure in which a portion of a second channel layer is buried. The semiconductor device configured to individually control the first and second channel layers.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: August 27, 2019
    Assignee: SK hynix Inc.
    Inventors: Dae Sung Eom, Jeong Sang Kang
  • Publication number: 20190148505
    Abstract: There are provided a semiconductor device and a manufacturing method thereof. The semiconductor device includes a pipe gate stack structure in which a portion of a first channel layer is buried. The semiconductor device includes the pipe gate stack structure in which a portion of a second channel layer is buried. The semiconductor device configured to individually control the first and second channel layers.
    Type: Application
    Filed: June 15, 2018
    Publication date: May 16, 2019
    Applicant: SK hynix Inc.
    Inventors: Dae Sung EOM, Jeong Sang KANG