Abstract: A three-dimensional memory device includes a stack structure including first and second tier stacks stacked on a substrate, each of the first and second tier stacks including a plurality of electrode layers and a plurality of interlayer insulating layers alternately stacked; a connection contact penetrating at least partially the stack structure; and a plurality of support patterns each including a first tier support penetrating the first tier stack and a second tier support penetrating the second tier stack. The plurality of support patterns include first support patterns adjacent to the connection contact. In two first support patterns among the first support patterns, which neighbor each other with the connection contact interposed therebetween, a gap between first tier supports is smaller than a gap between second tier supports.

Abstract: The present disclosure relates to a semiconductor device including a stress control insulating layer or a stress control pattern to control a stress applied to an interlayer insulating layer or a stacked body in a desirable direction.

Abstract: The present disclosure relates to a semiconductor device including a stress control insulating layer or a stress control pattern to control a stress applied to an interlayer insulating layer or a stacked body in a desirable direction.

Abstract: A nonvolatile memory device includes: a channel layer protruding perpendicular to a surface of a substrate; a tunnel insulation layer formed on a surface of the channel layer; a stack structure, in which a plurality of floating gate electrodes and a plurality of control gate electrodes are alternately formed along the channel layer; and a charge blocking layer interposed between each floating gate electrode, of the plurality of floating gate electrodes, and each control gate electrode of the plurality of control gate electrodes, wherein the floating gate electrode includes a first floating gate electrode between two control gate electrodes and a second floating gate electrode positioned in the lowermost and uppermost parts of the stack structure and having a smaller width in a direction parallel to the substrate than the first floating gate electrode.

Abstract: A nonvolatile memory device includes: a channel layer protruding perpendicular to a surface of a substrate; a tunnel insulation layer formed on a surface of the channel layer; a stack structure, in which a plurality of floating gate electrodes and a plurality of control gate electrodes are alternately formed along the channel layer; and a charge blocking layer interposed between each floating gate electrode, of the plurality of floating gate electrodes, and each control gate electrode of the plurality of control gate electrodes, wherein the floating gate electrode includes a first floating gate electrode between two control gate electrodes and a second floating gate electrode positioned in the lowermost and uppermost parts of the stack structure and having a smaller width in a direction parallel to the substrate than the first floating gate electrode.

Abstract: A nonvolatile memory device includes gate structures formed over a substrate, each gate structure including a tunnel insulating layer, a floating gate, an inter-gate dielectric layer, and a control gate that are sequentially stacked, a protective layer formed on sidewalls of the floating gate, and a second insulating layer covering the gate structures and having an air gap formed between the gate structures, wherein an adhesive strength between the second insulating layer and the protective layer is smaller than an adhesive strength between the second insulating layer and the gate structure.

Abstract: A nonvolatile memory device includes: a channel layer protruding perpendicular to a surface of a substrate; a tunnel insulation layer formed on a surface of the channel layer; a stack structure, in which a plurality of floating gate electrodes and a plurality of control gate electrodes are alternately formed along the channel layer; and a charge blocking layer interposed between each floating gate electrode, of the plurality of floating gate electrodes, and each control gate electrode of the plurality of control gate electrodes, wherein the floating gate electrode includes a first floating gate electrode between two control gate electrodes and a second floating gate electrode positioned in the lowermost and uppermost parts of the stack structure and having a smaller width in a direction parallel to the substrate than the first floating gate electrode.

Abstract: A nonvolatile memory device includes gate structures formed over a substrate, each gate structure including a tunnel insulating layer, a floating gate, an inter-gate dielectric layer, and a control gate that are sequentially stacked, a protective layer formed on sidewalls of the floating gate, and a second insulating layer covering the gate structures and having an air gap formed between the gate structures, wherein an adhesive strength between the second insulating layer and the protective layer is smaller than an adhesive strength between the second insulating layer and the gate structure.

Abstract: A nonvolatile memory device includes gate structures formed over a substrate, each gate structure including a tunnel insulating layer, a floating gate, an inter-gate dielectric layer, and a control gate that are sequentially stacked, a protective layer formed on sidewalls of the floating gate, and a second insulating layer covering the gate structures and having an air gap formed between the gate structures, wherein an adhesive strength between the second insulating layer and the protective layer is smaller than an adhesive strength between the second insulating layer and the gate structure.

Abstract: A nonvolatile memory device includes: a channel layer protruding perpendicular to a surface of a substrate; a tunnel insulation layer formed on a surface of the channel layer; a stack structure, in which a plurality of floating gate electrodes and a plurality of control gate electrodes are alternately formed along the channel layer; and a charge blocking layer interposed between each floating gate electrode, of the plurality of floating gate electrodes, and each control gate electrode of the plurality of control gate electrodes, wherein the floating gate electrode includes a first floating gate electrode between two control gate electrodes and a second floating gate electrode positioned in the lowermost and uppermost parts of the stack structure and having a smaller width in a direction parallel to the substrate than the first floating gate electrode.

Abstract: A semiconductor device includes an isolation trench formed in a semiconductor substrate; an isolation layer filling the isolation trench; and a first epitaxial layer interposed between the isolation layer and the semiconductor substrate, wherein a lattice structure of the semiconductor substrate has an angle difference from a lattice structure of the first epitaxial layer adjacent to the semiconductor substrate.