Abstract: A data storage device includes a controller configured to update an access request count and an access count corresponding to a target region based on an access request for the target region, and initialize the access count each time the access request count reaches a first threshold, and a nonvolatile memory apparatus including the target region, and configured to access the target region based on a control of the controller.

Abstract: A data storage device includes a controller configured to update an access request count and an access count corresponding to a target region based on an access request for the target region, and initialize the access count each time the access request count reaches a first threshold, and a nonvolatile memory apparatus including the target region, and configured to access the target region based on a control of the controller.

Abstract: An operating method of a data storage device including a plurality of nonvolatile memory devices includes the steps of: mapping physical addresses of the nonvolatile memory devices into logical addresses; reflecting environmental factors to remap a physical address into a logical address requested to be accessed; and performing an interleaving operation for the nonvolatile memory devices using the remapped physical address.

Abstract: Disclosed is a semiconductor memory device for controlling a memory block. The semiconductor memory device includes a plurality of memory blocks to store data, and controller. The memory controller requests a first memory block, of the plurality of memory blocks, to performing a copy operation to copy the first memory block to a second memory block of the plurality of memory blocks. The controller then requests the first memory block to perform an operation different than the copy operation. The controller then requests the memory block to stop the copy operation based on the to perform an operation different than the copy operation. Finally, the controller requests the memory block to resume the copy operation after the operation different than the copy operation is completed.

Abstract: An operating method of a data storage device including a plurality of nonvolatile memory devices includes the steps of: mapping physical addresses of the nonvolatile memory devices into logical addresses; reflecting environmental factors to remap a physical address into a logical address requested to be accessed; and performing an interleaving operation for the nonvolatile memory devices using the remapped physical address.

Abstract: A solid state storage system includes a flash memory area and a memory controller. The flash memory area includes memory blocks and replacement blocks configured to replace bad blocks occurring within the memory blocks. The memory controller is configured to perform a logical-to-physical address mapping on logical blocks including the replacement blocks, and select the replacement blocks using logical addresses of the logical blocks corresponding to the bad blocks.

Abstract: A solid state storage system includes a flash memory region comprising a plurality of memory blocks and a plurality of replacement blocks corresponding to error-occurred blocks when errors occur in the memory blocks; and a memory controller configured to perform a control operation to replace the error-occurred blocks with the replacement blocks, wherein the error-occurred blocks comprise correctable blocks and uncorrectable blocks, and wherein the memory controller determines whether the error-occurred blocks are the correctable blocks or the uncorrectable blocks and controls zones of the replacement blocks, replaced in correspondence to the correctable blocks, to be allocated a plurality of times.

Abstract: A semiconductor storage system includes a memory controller that classifies a memory block of a memory area into a data block and a buffer block. The buffer block corresponds to the data block. The memory controller compares the number of free pages of both the data block and the buffer block with the number of valid pages of the data block and the buffer block during mergence in order to select the merged target block. Depending on the result of the comparison, either the data block or the buffer block is selected as the merged target block.

Abstract: Solid-state storage systems and methods are provided for controlling a wear leveling process for uniform use of the memory cells that replaces worn memory blocks with less frequently used memory blocks. The wear leveling process is performed by changing the physical locations of the storage cells within each memory zone or plane. Reference values of target memory block erase counts and worn memory block erase counts are used for searching target memory blocks to be used as replacements.

Abstract: A non-volatile memory system includes a memory area including a plurality of non-volatile memory blocks, and a micro control unit configured to manage the memory blocks as a data block and a buffer block. As a write command is input, if no buffer block assigned to the data block exists and a free page exists in the data block, the micro control unit converts the data block to a self-buffer block.

Abstract: A nonvolatile memory apparatus includes: a memory controller coupled; and a memory area comprising a plurality of memory blocks controlled by the memory controller. The memory controller sets a plurality of physical blocks corresponding to the plurality of memory blocks, and sets a plurality of logical blocks which are mapping targets of the physical blocks such that a size of the logical blocks and a size of the physical blocks are asymmetrical.

Abstract: There is provided a method for controlling a nonvolatile memory apparatus in a nonvolatile memory system including a host interface, a memory controller, and a memory area. The method includes: checking a number of ECC fail bits, determining whether or not to replace a corresponding block, and replacing the block, while a read command provided from the host interface is performed; and replacing a block, which was not replaced during the read operation, with a block to be used as a replacement target during a write operation.

Abstract: A flash memory apparatus of an embodiment is configured to include a flash memory including a plurality of blocks and a read operation control circuit determining whether to replace a block in accordance with the number of times a read process is performed for each block of the plurality of blocks.

Abstract: A solid state storage system includes a flash memory region comprising a plurality of memory blocks and a plurality of replacement blocks corresponding to error-occurred blocks when errors occur in the memory blocks; and a memory controller configured to perform a control operation to replace the error-occurred blocks with the replacement blocks, wherein the error-occurred blocks comprise correctable blocks and uncorrectable blocks, and wherein the memory controller determines whether the error-occurred blocks are the correctable blocks or the uncorrectable blocks and controls zones of the replacement blocks, replaced in correspondence to the correctable blocks, to be allocated a plurality of times.

Abstract: Solid-state storage systems and methods are provided for controlling a wear leveling process for uniform use of the memory cells that replaces worn memory blocks with less frequently used memory blocks. The wear leveling process is performed by changing the physical locations of the storage cells within each memory zone or plane. Reference values of target memory block erase counts and worn memory block erase counts are used for searching target memory blocks to be used as replacements.

Abstract: A solid state storage system includes a flash memory area and a memory controller. The flash memory area includes memory blocks and replacement blocks configured to replace bad blocks occurring within the memory blocks. The memory controller is configured to perform a logical-to-physical address mapping on logical blocks including the replacement blocks, and select the replacement blocks using logical addresses of the logical blocks corresponding to the bad blocks.

Abstract: A semiconductor storage system includes a memory controller that classifies a memory block of a memory area into a data block and a buffer block. The buffer block corresponds to the data block. The memory controller compares the number of free pages of both the data block and the buffer block with the number of valid pages of the data block and the buffer block during mergence in order to select the merged target block. Depending on the result of the comparison, either the data block or the buffer block is selected as the merged target block.

Abstract: A flash memory apparatus of an embodiment is configured to include a flash memory including a plurality of blocks and a read operation control circuit determining whether to replace a block in accordance with the number of times a read process is performed for each block of the plurality of blocks.

Abstract: A solid state storage system is disclosed including a memory area having a plurality of chips. The solid state storage system includes a micro controller unit (MCU) configured to utilize the number of deletions for logical blocks corresponding to logical block addresses when performing wear leveling on the memory area. The allocation of the logical block addresses can be performed using an interleaving process and a multi-plane method. The solid state storage system performs global wear leveling by which the lifespan of the cells of the chips can be uniformly managed.

Abstract: A solid state storage system includes a memory area configured to include a plurality of chips, and a micro controller unit (MCU) configured to perform a control operation, such that continuous logical block addresses are allocated using a multi-plane method or an interleaving method to different chips, and a read/write operation is performed in the logical block address unit in response to a read/write command.