Abstract: A self refresh control device, for use in a semiconductor memory device, comprises a self refresh entry unit having at least one clock buffer for generating a self refresh entry signal in response to an external control signal, wherein the clock buffer generates a clock signal in response to an external clock signal and a clock buffer enable signal; a self refresh exit unit for generating a first self refresh exit signal in response to the external control signal and generating a second self refresh exit signal synchronized with the clock signal; a clock buffer controller for generating the clock buffer enable signal in response to the first self refresh exit signal; and a self refresh signal generator for generating a self refresh signal in response to the self refresh entry signal and the second self refresh exit signal.

Abstract: A self refresh control device, for use in a semiconductor memory device, comprises a self refresh entry unit having at least one clock buffer for generating a self refresh entry signal in response to an external control signal, wherein the clock buffer generates a clock signal in response to an external clock signal and a clock buffer enable signal; a self refresh exit unit for generating a first self refresh exit signal in response to the external control signal and generating a second self refresh exit signal synchronized with the clock signal; a clock buffer controller for generating the clock buffer enable signal in response to the first self refresh exit signal; and a self refresh signal generator for generating a self refresh signal in response to the self refresh entry signal and the second self refresh exit signal.

Abstract: The synchronous semiconductor memory device includes a frequency information generating circuit for outputting a plurality of frequency information corresponding to the frequency of the clock signal in response to a state control signal and an internal address in order to adjust a point of time to disable and precharge a word line by a frequency information corresponding to a frequency of a clock signal. Therefore, even though a high frequency clock signal is inputted, the word line is disabled and precharged when a cell node is charged enough. In this way, it can prevent from failing cell operations and promotes operation efficiency of the synchronous semiconductor memory device.

Abstract: A dual-level substrate voltage generator for generating a second voltage with a level higher than that of a first voltage and maintaining the level of the first voltage quickly and stably, thereby reducing sudden current dissipation during an active or pre-charge mode is disclosed. The dual-level substrate voltage generator includes a first substrate voltage generation block and a first voltage detecting block are used to provide the first substrate voltage at an optimum level. A second voltage generating block having a level lower than that of the first substrate voltage and a second voltage detecting block are used to provide the second substrate voltage at the optimum level to the second voltage generating block. A switching block divides a charge between the first and second substrate voltages.

Abstract: The synchronous semiconductor memory device includes a frequency information generating circuit for outputting a plurality of frequency information corresponding to the frequency of the clock signal in response to a state control signal and an internal address in order to adjust a point of time to disable and precharge a word line by a frequency information corresponding to a frequency of a clock signal. Therefore, even though a high frequency clock signal is inputted, the word line is disabled and precharged when a cell node is charged enough. In this way, it can prevent from failing cell operations and promotes operation efficiency of the synchronous semiconductor memory device.

Abstract: In a conventional voltage conversion circuit, a switching control unit for controlling a pumping operation to be alternately performed is decided by a delay of an inverter, and thus a switching timing is inefficiently considerably varied according to the delay. Also, a well bias is applied to prevent a switch from being latched up. However, a large layout area is required in order to generate the well bias. A voltage conversion circuit according to the present invention can reduce a layout area and power consumption and improve conductivity and reliability, by efficiently driving a pumping capacitor by receiving an oscillation signal during a voltage pumping operation and using transitions from high to low and from low to high without overlapping each driving signal through a flip-flop switching structure, and by solving reduction of a threshold voltage of an NMOS transistor by controlling a precharge and switching transistor with a PMOS transistor.

Abstract: A dual-level substrate voltage generator for generating a second voltage with a level higher than that of a first voltage and maintaining the level of the first voltage quickly and stably, thereby reducing sudden current dissipation during an active or pre-charge mode is disclosed. The dual-level substrate voltage generator includes a first substrate voltage generation block and a first voltage detecting block are used to provide the first substrate voltage at an optimum level. A second voltage generating block having a level lower than that of the first substrate voltage and a second voltage detecting block are used to provide the second substrate voltage at the optimum level to the second voltage generating block. A switching block divides a charge between the first and second substrate voltages.

Abstract: A hierarchical word line structure for a semiconductor memory is provided that substantially eliminates coupling noise between neighboring wiring lines by driving neighboring sub-word lines by different main word lines. The hierarchical word line structure further reduces a layout size. The hierarchical word line structure uses one less transistor than a related art sub-word line driver. The word line includes a plurality of word line rows that each include a plurality of sub-word line drivers. The sub-word line drivers receive sub-word line driver enable signals among which only one signal becomes high level at a time. Each of the word line rows correspond to a main word line and a subset of the plurality of sub-word line drivers that drive neighboring sub-word lines are coupled to different respective main word lines.