Abstract: A memory controller controlling an operation of a memory device includes a parity module configured to perform one or more exclusive OR operations using data to be stored in the memory device and generate parity according to the one or more exclusive OR operations, and a recovery controller configured to control the parity module to store the parity in the memory device based on the number of times the exclusive OR operation is performed.

Abstract: The present technology includes a memory controller and a method of operating the same. The memory controller controlling an operation of a memory device includes a parity module configured to perform one or more exclusive OR operations using data to be stored in the memory device and generate parity according to the one or more exclusive OR operations, and a recovery controller configured to control the parity module to store the parity in the memory device based on the number of times the exclusive OR operation is performed.

Abstract: A power-supply device and an electronic device including the relate to technology for a data storage device. The electronic device includes a power-supply device and a controller. The power-supply device generates a sudden power loss (SPL) detection signal in a sudden power off (SPO) state by detecting a level of an external power, generates a charging sense signal indicative of a charging capacity of an auxiliary power-supply circuit, divides the charging capacity into a plurality of charging levels, detects a level of the charging capacity, and generates a charging sense signal indicating a charging level of the auxiliary power-supply circuit in response to the detected charging level. The controller stores flushing information in at least one non-volatile memory device when the SPL detection signal is activated, and variably adjust an amount of storage in the non-volatile memory device in response to the charging sense signal.

Abstract: A power-supply device and an electronic device including the relate to technology for a data storage device. The electronic device includes a power-supply device and a controller. The power-supply device generates a sudden power loss (SPL) detection signal in a sudden power off (SPO) state by detecting a level of an external power, generates a charging sense signal indicative of a charging capacity of an auxiliary power-supply circuit, divides the charging capacity into a plurality of charging levels, detects a level of the charging capacity, and generates a charging sense signal indicating a charging level of the auxiliary power-supply circuit in response to the detected charging level. The controller stores flushing information in at least one non-volatile memory device when the SPL detection signal is activated, and variably adjust an amount of storage in the non-volatile memory device in response to the charging sense signal.

Abstract: A power-supply device and an electronic device including the relate to technology for a data storage device. The electronic device includes a power-supply device and a controller. The power-supply device generates a sudden power loss (SPL) detection signal in a sudden power off (SPO) state by detecting a level of an external power, generates a charging sense signal indicative of a charging capacity of an auxiliary power-supply circuit, divides the charging capacity into a plurality of charging levels, detects a level of the charging capacity, and generates a charging sense signal indicating a charging level of the auxiliary power-supply circuit in response to the detected charging level. The controller stores flushing information in at least one non-volatile memory device when the SPL detection signal is activated, and variably adjust an amount of storage in the non-volatile memory device in response to the charging sense signal.

Abstract: A power-supply device and an electronic device including the relate to technology for a data storage device. The electronic device includes a power-supply device and a controller. The power-supply device generates a sudden power loss (SPL) detection signal in a sudden power off (SPO) state by detecting a level of an external power, generates a charging sense signal indicative of a charging capacity of an auxiliary power-supply circuit, divides the charging capacity into a plurality of charging levels, detects a level of the charging capacity, and generates a charging sense signal indicating a charging level of the auxiliary power-supply circuit in response to the detected charging level. The controller stores flushing information in at least one non-volatile memory device when the SPL detection signal is activated, and variably adjust an amount of storage in the non-volatile memory device in response to the charging sense signal.

Abstract: A power-supply device and an electronic device including the relate to technology for a data storage device. The electronic device includes a power-supply device and a controller. The power-supply device generates a sudden power loss (SPL) detection signal in a sudden power off (SPO) state by detecting a level of an external power, generates a charging sense signal indicative of a charging capacity of an auxiliary power-supply circuit, divides the charging capacity into a plurality of charging levels, detects a level of the charging capacity, and generates a charging sense signal indicating a charging level of the auxiliary power-supply circuit in response to the detected charging level. The controller stores flushing information in at least one non-volatile memory device when the SPL detection signal is activated, and variably adjust an amount of storage in the non-volatile memory device in response to the charging sense signal.

Abstract: A semiconductor device includes a cell mask pattern disposed in a cell region of a mask substrate and a vernier mask pattern disposed in a vernier region of the mask substrate. The vernier mask pattern includes a variable mask pattern portion to transfer a different shape of pattern depending on the magnitude of exposure energy.

Abstract: A semiconductor device includes a cell mask pattern disposed in a cell region of a mask substrate and a vernier mask pattern disposed in a vernier region of the mask substrate. The vernier mask pattern includes a variable mask pattern portion to transfer a different shape of pattern depending on the magnitude of exposure energy.

Abstract: An image sensor includes a trench formed in a semiconductor substrate, a first reflection part formed in the trench and having an inclined, curved surface, a second reflection part formed on the first reflection part such that a remaining space of the trench is filled with the second reflection part, and a vertical type photodiode formed on a region of the substrate between trenches. A method for forming the image sensor includes forming a trench in a semiconductor substrate, forming a first reflection part having an inclined, curved surface in the trench, forming a second reflection part on the first reflection part such that a remaining space of the trench is filled with the second reflection part, and forming a vertical type photodiode on a region of the substrate between trenches.

Abstract: An apparatus to obtain 3D location information from an image using a single camera or sensor includes a first table, in which the numbers of pixels are recorded according to the distance of a reference object. Using the prepared first table and a determined focal distance, a second table is generated in which the number of pixels is recorded according to the distance of a target object. Distance information is then calculated according to the detected number of pixels with reference to the second table. A method for obtaining 3D location information includes detecting a number of pixels of a target object from a first image, generating tables including numbers of pixels according to distance, detecting a central pixel and a number of pixels of the target object from a second image, and estimating two-dimensional location information one-dimensional distance of the target object from the tables and pixel information.

Abstract: An image sensor and manufacturing method thereof are provided. A semiconductor substrate can include a light blocking region and a light receiving region. A photodiode can be formed in the light blocking region and in the light receiving region. A gate can be disposed at a side of the photodiode in the light receiving region, and a light blocking gate can be disposed on the photodiode in the light blocking region. A salicide layer can be formed on the light blocking gate.

Abstract: A CMOS image sensor and a fabricating method for a semiconductor device are disclosed. Embodiments provide a CMOS image sensor having an improved structure using a light reflection system, with a fabricating method thereof to simplify the fabrication process and maximize a light receiving area. Embodiments may be applied to a semiconductor device having a lamination structure.

Abstract: An image sensor including a first epitaxial layer formed over a semiconductor substrate; first photodiodes formed spaced apart in the first epitaxial layer; a first isolation region electrically isolating the first photodiodes from each other; a second epitaxial layer formed over the first epitaxial layer; second photodiodes formed spaced apart in the second epitaxial layer; and a second isolation region electrically isolating the second photodiodes from each other.

Abstract: A method for manufacturing a vertical CMOS image sensor related to a semiconductor device is disclosed. A high-temperature double annealing process and/or an additional passivation nitride film are selectively applied in order to improve dark leakage characteristics and also to prevent or reduce an incidence of circular defects, thereby enhancing the quality and reliability of the vertical CMOS image sensor.

Abstract: A method of manufacturing a complimentary metal oxide semiconductor (CMOS) image sensor. The method includes a step of performing a silicide process relative to a plug for transferring electrons generated from a photodiode. The silicide of the plug blocks light irradiated through the plug, so that the performance of the image sensor may be optimized.

Abstract: An image sensor includes a trench formed in a semiconductor substrate, a first reflection part formed in the trench and having an inclined, curved surface, a second reflection part formed on the first reflection part such that a remaining space of the trench is filled with the second reflection part, and a vertical type photodiode formed on a region of the substrate between trenches. A method for forming the image sensor includes forming a trench in a semiconductor substrate, forming a first reflection part having an inclined, curved surface in the trench, forming a second reflection part on the first reflection part such that a remaining space of the trench is filled with the second reflection part, and forming a vertical type photodiode on a region of the substrate between trenches.

Abstract: Embodiments relate to an image sensor and a method for manufacturing an image sensor that may prevent a photoresist pattern from remaining on gates by forming a floating diffusion area faster than the gates. According to embodiments, since the gates may not be influenced by an ion implantation process, current characteristics and operation reliability may be enhanced. According to embodiments, the method may include forming dummy ion implantation mask patterns for forming a floating diffusion area over an epitaxial layer and forming an ion implantation mask pattern over the epitaxial layer and at least a portion of the dummy ion implantation mask patterns, so as to form the floating diffusion area by performing an ion implantation process.

Abstract: A method for manufacturing an image sensor that can include forming a pad electrode over a semiconductor substrate; forming a protective layer over the pad electrode; forming a via hole through the protective layer to expose a portion of the uppermost surface of the pad electrode; and then forming a gold layer over the exposed portion of the uppermost surface of the pad electrode.

Abstract: A complementary metal oxide semiconductor (CMOS) image sensor including a semiconductor substrate having an inclined groove with an inclined surface and a light reception surface perpendicular to the semiconductor substrate, and a device forming area adjacent the light reception surface. A reflection film selectively formed on and/or over the inclined surface, a plurality of photodiodes substantially perpendicular to the surface of the substrate; and at least one MOS transistor formed on the surface of the device forming area.