Patents by Inventor Jeong Sub LIM

Jeong Sub LIM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Pattern forming method and semiconductor device manufacturing method using the same
    Patent number: 9941285
    Abstract: A method for forming patterns includes forming an etch target layer; etching the etch target layer to form a pre-pattern having a line forming portion and a plurality of pad portions; forming a plurality of spacers which extend across the pad portions and the line forming portion; forming, over the spacers, a blocking layer having an opening which blocks the pad portions and exposes the line forming portion; and etching the line forming portion by using the blocking layer and the spacers as a barrier, to form a plurality of line portions.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: April 10, 2018
    Assignee: SK Hynix Inc.
    Inventors: Jae-Houb Chun, Jeong-Sub Lim
  • PATTERN FORMING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD USING THE SAME
    Publication number: 20170352667
    Abstract: A method for forming patterns includes forming an etch target layer; etching the etch target layer to form a pre-pattern having a line forming portion and a plurality of pad portions; forming a plurality of spacers which extend across the pad portions and the line forming portion; forming, over the spacers, a blocking layer having an opening which blocks the pad portions and exposes the line forming portion; and etching the line forming portion by using the blocking layer and the spacers as a barrier, to form a plurality of line portions.
    Type: Application
    Filed: August 25, 2017
    Publication date: December 7, 2017
    Inventors: Jae-Houb CHUN, Jeong-Sub LIM
  • Dummy bit line MOS capacitor and device using the same
    Patent number: 9825146
    Abstract: A MOS capacitor, a method of fabricating the same, and a semiconductor device using the same are provided. The MOS capacitor is arranged in an outermost cell block of the semiconductor device employing an open bit line structure. The MOS capacitor includes a first electrode arranged in a semiconductor substrate, a dielectric layer arranged on a semiconductor substrate, and a second electrode arranged on the dielectric layer and including a dummy bit line.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: November 21, 2017
    Assignee: SK HYNIX INC.
    Inventor: Jeong Sub Lim
  • Pattern forming method and semiconductor device manufacturing method using the same
    Patent number: 9780095
    Abstract: A method for forming patterns includes forming an etch target layer; etching the etch target layer to form a pre-pattern having a line forming portion and a plurality of pad portions; forming a plurality of spacers which extend across the pad portions and the line forming portion; forming, over the spacers, a blocking layer having an opening which blocks the pad portions and exposes the line forming portion; and etching the line forming portion by using the blocking layer and the spacers as a barrier, to form a plurality of line portions.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: October 3, 2017
    Assignee: SK Hynix Inc.
    Inventors: Jae-Houb Chun, Jeong-Sub Lim
  • PATTERN FORMING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD USING THE SAME
    Publication number: 20170243871
    Abstract: A method for forming patterns includes forming an etch target layer; etching the etch target layer to form a pre-pattern having a line forming portion and a plurality of pad portions; forming a plurality of spacers which extend across the pad portions and the line forming portion; forming, over the spacers, a blocking layer having an opening which blocks the pad portions and exposes the line forming portion; and etching the line forming portion by using the blocking layer and the spacers as a barrier, to form a plurality of line portions.
    Type: Application
    Filed: July 7, 2016
    Publication date: August 24, 2017
    Inventors: Jae-Houb CHUN, Jeong-Sub LIM
  • DUMMY BIT LINE MOS CAPACITOR AND DEVICE USING THE SAME
    Publication number: 20160087072
    Abstract: A MOS capacitor, a method of fabricating the same, and a semiconductor device using the same are provided. The MOS capacitor is arranged in an outermost cell block of the semiconductor device employing an open bit line structure. The MOS capacitor includes a first electrode arranged in a semiconductor substrate, a dielectric layer arranged on a semiconductor substrate, and a second electrode arranged on the dielectric layer and including a dummy bit line.
    Type: Application
    Filed: December 7, 2015
    Publication date: March 24, 2016
    Inventor: Jeong Sub LIM
  • Dummy bit line MOS capacitor and device using the same
    Patent number: 9236501
    Abstract: A MOS capacitor, a method of fabricating the same, and a semiconductor device using the same are provided. The MOS capacitor is arranged in an outermost cell block of the semiconductor device employing an open bit line structure. The MOS capacitor includes a first electrode arranged in a semiconductor substrate, a dielectric layer arranged on a semiconductor substrate, and a second electrode arranged on the dielectric layer and including a dummy bit line.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: January 12, 2016
    Assignee: SK HYNIX INC.
    Inventor: Jeong Sub Lim
  • MOS CAPACITOR, METHOD OF FABRICATING THE SAME, AND SEMICONDUCTOR DEVICE USING THE SAME
    Publication number: 20140021521
    Abstract: A MOS capacitor, a method of fabricating the same, and a semiconductor device using the same are provided. The MOS capacitor is arranged in an outermost cell block of the semiconductor device employing an open bit line structure. The MOS capacitor includes a first electrode arranged in a semiconductor substrate, a dielectric layer arranged on a semiconductor substrate, and a second electrode arranged on the dielectric layer and including a dummy bit line.
    Type: Application
    Filed: December 3, 2012
    Publication date: January 23, 2014
    Applicant: SK HYNIX INC.
    Inventor: Jeong Sub LIM