Abstract: A display device includes a gate electrode on a substrate of a semiconductor device, a gate insulating film over the gate electrode, an active layer comprising an oxide including indium, zinc and gallium on the gate insulating film, and overlapping the gate electrode, and a source electrode and a drain electrode that are spaced apart from each other, wherein the active layer is formed from a zinc-rich target material, and an atomic % ratio of indium, zinc and gallium in the active layer is different from an atomic % ratio of the zinc-rich target material.

Abstract: A display device includes a gate electrode on a substrate of a semiconductor device, a gate insulating film over the gate electrode, an active layer comprising an oxide including indium, zinc and gallium on the gate insulating film, and overlapping the gate electrode, and a source electrode and a drain electrode that are spaced apart from each other, wherein the active layer is formed from a zinc-rich target material, and an atomic % ratio of indium, zinc and gallium in the active layer is different from an atomic % ratio of the zinc-rich target material.

Abstract: A method for manufacturing a semiconductor device is discussed. The method includes forming a gate electrode on a substrate, forming a gate insulating film over the substrate, depositing an In—Ga—Zn oxide over the gate insulating film while heating the substrate to a temperature of 200 to 300° C., an atomic percent ratio of Zn in the In—Ga—Zn oxide as-deposited being higher than that of In or Ga, heat-treating the deposited In—Ga—Zn oxide at a temperature of 200 to 350° C., thereby forming an active layer crystallized throughout an entire thickness of the active layer, and forming a source electrode and a drain electrode.

Abstract: A method for manufacturing a semiconductor device is discussed. The method includes forming a gate electrode on a substrate, forming a gate insulating film over the substrate, depositing an In—Ga—Zn oxide over the gate insulating film while heating the substrate to a temperature of 200 to 300° C., an atomic percent ratio of Zn in the In—Ga—Zn oxide as-deposited being higher than that of In or Ga, heat-treating the deposited In—Ga—Zn oxide at a temperature of 200 to 350° C., thereby forming an active layer crystallized throughout an entire thickness of the active layer, and forming a source electrode and a drain electrode.

Abstract: An oxide semiconductor crystallization method may include depositing an In—Ga—Zn oxide over the substrate while heating a substrate to a temperature of 200 to 300° C., and heat-treating the deposited In—Ga—Zn oxide at a temperature of 200 to 350° C., thereby forming an oxide semiconductor layer crystallized throughout an entire thickness thereof.

Abstract: An oxide semiconductor crystallization method may include depositing an In—Ga—Zn oxide over the substrate while heating a substrate to a temperature of 200 to 300° C., and heat-treating the deposited In—Ga—Zn oxide at a temperature of 200 to 350° C., thereby forming an oxide semiconductor layer crystallized throughout an entire thickness thereof.

Abstract: A method for manufacturing a thin film transistor (TFT) array substrate having enhanced reliability is disclosed. The method includes forming a multilayer structure including at least one first metal layer and a second metal layer made of copper, forming a first mask layer including a first mask area corresponding to a data line and a second mask area corresponding to an electrode pattern to overlap with an active layer, patterning the multilayer structure, thereby forming the data line constituted by the multilayer structure, patterning the second metal layer, thereby forming the electrode pattern constituted by the at least one first metal layer, forming a second mask layer to expose a portion of the electrode pattern corresponding to a channel area of the active layer, patterning the at least one first metal layer, thereby forming source and drain.

Abstract: A method for manufacturing a thin film transistor (TFT) array substrate having enhanced reliability is disclosed. The method includes forming a multilayer structure including at least one first metal layer and a second metal layer made of copper, forming a first mask layer including a first mask area corresponding to a data line and a second mask area corresponding to an electrode pattern to overlap with an active layer, patterning the multilayer structure, thereby forming the data line constituted by the multilayer structure, patterning the second metal layer, thereby forming the electrode pattern constituted by the at least one first metal layer, forming a second mask layer to expose a portion of the electrode pattern corresponding to a channel area of the active layer, patterning the at least one first metal layer, thereby forming source and drain.

Abstract: Embodiments of the invention provide a column address strobe (CAS) latency circuit that generates a stable latency signal in a high-speed semiconductor memory device, and a semiconductor memory device including the CAS latency circuit. The CAS latency circuit may include an internal read command signal generator and a latency clock generator coupled to a latency signal generator. In an embodiment of the invention, the latency signal generator outputs a stable latency signal by shifting an internal read signal output from the internal read command signal generator based on latency control clocks output from the latency clock generator.

Abstract: A semiconductor device according to example embodiments that may include an on-die termination (ODT) control circuit having a pipe line structure which changes in response to a frequency of a clock signal and a termination resistance generator for generating termination resistance in response to a termination resistance control signal.

Abstract: A semiconductor device according to example embodiments that may include an on-die termination (ODT) control circuit having a pipe line structure which changes in response to a frequency of a clock signal and a termination resistance generator for generating termination resistance in response to a termination resistance control signal.

Abstract: Embodiments of the invention provide a column address strobe (CAS) latency circuit that generates a stable latency signal in a high-speed semiconductor memory device, and a semiconductor memory device including the CAS latency circuit. The CAS latency circuit may include an internal read command signal generator and a latency clock generator coupled to a latency signal generator. In an embodiment of the invention, the latency signal generator outputs a stable latency signal by shifting an internal read signal output from the internal read command signal generator based on latency control clocks output from the latency clock generator.

Abstract: An output impedance control circuit of a semiconductor device. A first transistor is connected to a pad and a level controller controls a gate voltage of the first transistor in response to a voltage of the pad and a reference voltage. A MOS array is connected between the pad and a power supply voltage and supplies current to the pad in response to an impedance control code. A first control circuit generates the impedance control code in response to whether a voltage of the pad is converging to the reference voltage. A second control circuit controls a pull-up impedance of the output buffer circuit in response to the first impedance control code when a voltage of the pad is converging to the reference voltage.

Abstract: An output impedance control circuit of a semiconductor device. A first transistor is connected to a pad and a level controller controls a gate voltage of the first transistor in response to a voltage of the pad and a reference voltage. A MOS array is connected between the pad and a power supply voltage and supplies current to the pad in response to an impedance control code. A first control circuit generates the impedance control code in response to whether a voltage of the pad is converging to the reference voltage. A second control circuit controls a pull-up impedance of the output buffer circuit in response to the first impedance control code when a voltage of the pad is converging to the reference voltage.