Abstract: A method and device for recovering data in a non-volatile semiconductor memory device that may include controlling a reference current by the non-volatile semiconductor memory device, reading data of at least one memory cell based on the controlled reference current, storing the read data in a buffer memory, and writing the data stored in the buffer memory to the at least one memory cell.

Abstract: A nonvolatile semiconductor memory device may include a cell array and a program modulation unit. The cell array may further include a plurality of word lines, a plurality of bit lines, a plurality of cell transistors and a plurality of source lines. The plurality of bit lines may intersect the plurality of word lines. The plurality of cell transistors may be arranged at intersections of the word lines and bit lines, and may have drains and gates connected to the bit lines and the word lines, respectively. The source lines may be connected to sources of the plurality of cell transistors. The program-voltage modulation unit may modulate a program voltage based on a number of cell transistors selected for programming.

Abstract: An e-fuse adapted to indicate programming state in relation leakage current path defined by a program transistor both before and after dielectric breakdown has occurred. The e-fuse comprises: a program circuit including the program transistor, a switch circuit connected between the program circuit and ground, a current supply circuit connected to the program circuit and supplying a predetermined current to the leakage current path after the program transistor is programmed; and a sense/amplification circuit connected to a program node associated with the leakage current path and adapted to sense and output the programming state.

Abstract: A memory device includes a flash memory cell array comprising a plurality of flash memory cells, a program voltage generator circuit configured to generate a program voltage at an output thereof and a program circuit coupled to the output of the program voltage generator circuit and configured to couple the output of the program voltage generator circuit to the memory cell array. The memory cell array responsively loads the output of the program voltage generator circuit an amount that varies in correlation with data applied to the memory cell array. The device further includes a program current compensator circuit coupled to the output of the program voltage generator circuit and configured to load the program voltage generator circuit in correlation to the data applied to the memory cell array.

Abstract: A method and device for recovering data in a non-volatile semiconductor memory device that may include controlling a reference current by the non-volatile semiconductor memory device, reading data of at least one memory cell based on the controlled reference current, storing the read data in a buffer memory, and writing the data stored in the buffer memory to the at least one memory cell.

Abstract: In a sense amplifier and method of generating a variable reference level, the sense amplifier varies a reference voltage level in accordance with variation of a operating voltage. This ensures that on-cell and off-cell margins required to detect data are sufficiently maintained regardless of the variation of the operating voltage in the semiconductor memory device. Read failures that otherwise would be generated due to insufficient voltage sensing margin are thus avoided.

Abstract: A memory device includes a flash memory cell array comprising a plurality of flash memory cells, a program voltage generator circuit configured to generate a program voltage at an output thereof and a program circuit coupled to the output of the program voltage generator circuit and configured to couple the output of the program voltage generator circuit to the memory cell array. The memory cell array responsively loads the output of the program voltage generator circuit an amount that varies in correlation with data applied to the memory cell array. The device further includes a program current compensator circuit coupled to the output of the program voltage generator circuit and configured to load the program voltage generator circuit in correlation to the data applied to the memory cell array.

Abstract: A nonvolatile semiconductor memory device may include a cell array and a program modulation unit. The cell array may further include a plurality of word lines, a plurality of bit lines, a plurality of cell transistors and a plurality of source lines. The plurality of bit lines may intersect the plurality of word lines. The plurality of cell transistors may be arranged at intersections of the word lines and bit lines, and may have drains and gates connected to the bit lines and the word lines, respectively. The source lines may be connected to sources of the plurality of cell transistors. The program-voltage modulation unit may modulate a program voltage based on a number of cell transistors selected for programming.

Abstract: An e-fuse adapted to indicate programming state in relation leakage current path defined by a program transistor both before and after dielectric breakdown has occurred. The e-fuse comprises: a program circuit including the program transistor, a switch circuit connected between the program circuit and ground, a current supply circuit connected to the program circuit and supplying a predetermined current to the leakage current path after the program transistor is programmed; and a sense/amplification circuit connected to a program node associated with the leakage current path and adapted to sense and output the programming state.

Abstract: In a sense amplifier and method of generating a variable reference level, the sense amplifier varies a reference voltage level in accordance with variation of a operating voltage. This ensures that on-cell and off-cell margins required to detect data are sufficiently maintained regardless of the variation of the operating voltage in the semiconductor memory device. Read failures that otherwise would be generated due to insufficient voltage sensing margin are thus avoided.

Abstract: Integrated circuit devices include a comparator circuit and a fuse programmable input circuit. The fuse programmable input circuit generates first and second differential input signals at voltage levels that can be controlled through a pair of fuses. The comparator circuit generates an output signal based on the relative voltage levels exhibited by the first and second differential input signals. In particular, the output signal is driven to a first logic state when the voltage difference between the first and second differential input signals is positive and the output signal is driven to a second logic state, which is opposite the first logic state, when the voltage difference is negative. Because the comparator is responsive to the relative difference between the voltage levels of the first and second differential input signals and not the absolute magnitudes of the voltage levels, fuse remnants that may exist after the fuse programmable input circuit has been programmed (i.e.