Patents by Inventor Jeong-Youb Lee
Jeong-Youb Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6879006Abstract: A method for fabricating a CMOS transistor is disclosed. The present invention provides a method for producing a CMOS transistor having enhanced performance since a short channel characteristic and operation power can be controlled by the duplicate punch stop layer of the pMOS region and the operation power of the nMOS is also controlled by dopant concentration of the duplicated LDD region combined by the first LDD region and the second LDD region.Type: GrantFiled: March 26, 2004Date of Patent: April 12, 2005Assignee: Hynix Semiconductor Inc.Inventors: Yong-Sun Sohn, Chang-Woo Ryoo, Jeong-Youb Lee
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Publication number: 20040180489Abstract: A method for fabricating a CMOS transistor is disclosed. The present invention provides a method for producing a CMOS transistor having enhanced performance since a short channel characteristic and operation power can be controlled by the duplicate punch stop layer of the pMOS region and the operation power of the nMOS is also controlled by dopant concentration of the duplicated LDD region combined by the first LDD region and the second LDD region.Type: ApplicationFiled: March 26, 2004Publication date: September 16, 2004Applicant: Hynix Semiconductor Inc.Inventors: Yong-Sun Sohn, Chang-Woo Ryoo, Jeong-Youb Lee
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Patent number: 6767780Abstract: A method for fabricating a CMOS transistor is disclosed. The present invention provides a method for producing a CMOS transistor having enhanced performance since a short channel characteristic and operation power can be controlled by the duplicate punch stop layer of the pMOS region and the operation power of the nMOS is also controlled by dopant concentration of the duplicated LDD region combined by the first LDD region and the second LDD region.Type: GrantFiled: December 31, 2002Date of Patent: July 27, 2004Assignee: Hynix Semiconductor Inc.Inventors: Yong-Sun Sohn, Chang-Woo Ryoo, Jeong-Youb Lee
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Patent number: 6667200Abstract: A method for forming a transistor of a semiconductor device, including the step of forming channel layers of a first and a second conductive types, performing high temperature thermal process to form stabilized channel layers and forming an epitaxial channel structure having a super-steep-retrograde &dgr;-doped layer by growing undoped silicon epitaxial layers, treating the entire surface of the resulting structure with hydrogen, forming an epitaxial channel structure by growing undoped silicon epitaxial layers on the stabilized channel layers, forming gate insulating films and gate electrodes on the epitaxial channel structures, re-oxidizing the gate insulating films for repairing damaged portions of the gate insulating films; and forming a source/drain region and performing a low temperature thermal process.Type: GrantFiled: December 30, 2002Date of Patent: December 23, 2003Assignee: Hynix Semiconductor Inc.Inventors: Yong Sun Sohn, Chang Woo Ryoo, Jeong Youb Lee
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Patent number: 6667233Abstract: A method for forming a silicide layer of a semiconductor memory device is disclosed. A silicide layer is formed in an impurity junction region through a contact hole exposing the impurity junction region on a semiconductor substrate. Here, two thermal annealing processes are performed on the semiconductor substrate on which a metal layer is deposited, by using low and high temperature up speeds and maintaining the semiconductor substrate under the highest temperature for less than one second, and then dropping the temperature at high speed. The process for removing a portion of the metal layer which did not react is carried out. As a result, a shallow junction can be formed in a very small devices, and deterioration of an electrical property of the semiconductor device is minimized by reducing junction leakage current, which results in the rapid operation of the device.Type: GrantFiled: December 24, 2002Date of Patent: December 23, 2003Assignee: Hynix Semiconductor IncInventors: Chang Woo Ryoo, Jeong Youb Lee, Yong Sun Sohn
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Publication number: 20030218219Abstract: A method for fabricating a CMOS transistor is disclosed. The present invention provides a method for producing a CMOS transistor having enhanced performance since a short channel characteristic and operation power can be controlled by the duplicate punch stop layer of the pMOS region and the operation power of the nMOS is also controlled by dopant concentration of the duplicated LDD region combined by the first LDD region and the second LDD region.Type: ApplicationFiled: December 31, 2002Publication date: November 27, 2003Inventors: Yong-Sun Sohn, Chang-Woo Ryoo, Jeong-Youb Lee
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Publication number: 20030215992Abstract: A method for forming a transistor of a semiconductor device, including the step of forming a channel layers of a first and a second conductive types, performing high temperature thermal process to form stabilized channel layers and forming an epitaxial channel structure having a super-steep-retrograde &dgr;-doped layer by growing undoped silicon epitaxial layers, treating the entire surface of the resulting structure with hydrogen, forming an epitaxial channel structure by growing undoped silicon epitaxial layers on the stabilized channel layers, forming gate insulating films and gate electrodes on the epitaxial channel structures, re-oxidizing the gate insulating films for repairing damaged portions of the gate insulating films; and forming a source/drain region and performing a low temperature thermal process.Type: ApplicationFiled: December 30, 2002Publication date: November 20, 2003Inventors: Yong Sun Sohn, Chang Woo Ryoo, Jeong Youb Lee
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Patent number: 6586288Abstract: A method of forming dual-metal gates in a semiconductor device, including the steps of providing a semiconductor substrate having a PMOS area and an NMOS area wherein dummy gates are formed in the PMOS and NMOS areas respectively, forming an insulating interlayer on the semiconductor substrate so as to cover the dummy gates, polishing the insulating interlayer until the dummy gates are exposed, forming a first groove defining a first metal gate area by selectively removing one of the dummy gates formed in the PMOS and NMOS areas, forming a first gate insulating layer and a first metal layer on an entire area of the semiconductor substrate including the first groove successively, forming a first metal gate in the first groove by etching the first metal layer and first gate insulating layer until the insulating interlayer is exposed, forming a second groove defining a second metal gate area by removing the remaining dummy gate, forming a second gate insulating layer and a second metal layer on the entire area oType: GrantFiled: October 18, 2001Date of Patent: July 1, 2003Assignee: Hynix Semiconductor Inc.Inventors: Tae Kyun Kim, Tae Ho Cha, Jeong Youb Lee, Se Aug Jang
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Publication number: 20030119309Abstract: A method for forming a suicide layer of a semiconductor memory device is disclosed. A silicide layer is formed in an impurity junction region through a contact hole exposing the impurity junction region on a semiconductor substrate. Here, two thermal annealing processes are performed on the semiconductor substrate on which a metal layer is deposited, by using low and high temperature up speeds and maintaining the semiconductor substrate under the highest temperature for less than one second, and then dropping the temperature at high speed. The process for removing a portion of the metal layer which did not react is carried out. As a result, a shallow junction can be formed in a very small devices, and deterioration of an electrical property of the semiconductor device is minimized by reducing junction leakage current, which results in the rapid operation of the device.Type: ApplicationFiled: December 24, 2002Publication date: June 26, 2003Inventors: Chang Woo Ryoo, Jeong Youb Lee, Yong Sun Sohn
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Patent number: 6579767Abstract: A method for forming a gate structure begins by preparing a semiconductor substrate provided with an isolation region formed therein. A thin SiO2 layer is thermally grown on top of the semiconductor device by using a wet H2/O2 or a dry O2. And then, an aluminum oxide layer is formed on top of the semiconductor substrate with doping a dopant in situ. A conductive layer is formed on top of the Al2O3 layer. Finally, the conductive layer and the Al2O3 layer are patterned into the gate structure. The dopant is a material selected from a group consisting of Si, Zr, Hf, Nb or the like.Type: GrantFiled: December 4, 2000Date of Patent: June 17, 2003Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Dae-Gyu Park, Se-Aug Jang, Jeong-Youb Lee, Hung-Jae Cho, Jung-Ho Kim
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Patent number: 6524918Abstract: A method for forming a gate structure begins by preparing a semiconductor substrate provided with an isolation region formed therein. An aluminum oxide (Al2O3) layer is deposited on top of the semiconductor substrate and then, silicon ions plasma doping is carried out. Thereafter, the Al2O3 layer doped with silicon ions is annealed in the presence of oxygen gas or nitrous oxygen to remove a metallic vacancy in the Al2O3 layer. Subsequently, a conductive layer is formed on top of the Al2O3 layer. Finally, the conductive layer is patterned into the gate structure.Type: GrantFiled: December 19, 2000Date of Patent: February 25, 2003Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Dae-Gyu Park, Se-Aug Jang, Jeong-Youb Lee
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Publication number: 20020058374Abstract: A method of forming dual-metal gates in a semiconductor device, including the steps of providing a semiconductor substrate having a PMOS area and an NMOS area wherein dummy gates are formed in the PMOS and NMOS areas respectively, forming an insulating interlayer on the semiconductor substrate so as to cover the dummy gates, polishing the insulating interlayer until the dummy gates are exposed, forming a first groove defining a first metal gate area by selectively removing one of the dummy gates formed in the PMOS and NMOS areas, forming a first gate insulating layer and a first metal layer on an entire area of the semiconductor substrate including the first groove successively, forming a first metal gate in the first groove by etching the first metal layer and first gate insulating layer until the insulating interlayer is exposed, forming a second groove defining a second metal gate area by removing the remaining dummy gate, forming a second gate insulating layer and a second metal layer on the entire area oType: ApplicationFiled: October 18, 2001Publication date: May 16, 2002Inventors: Tae-Kyun Kim, Tae ho Cha, Jeong Youb Lee, Se Aug Jang
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Publication number: 20010040292Abstract: During selective epitaxial growth processing using LPCVD equipment, a SiGe epitaxial layer and a Si epitaxial layer are sequentially formed so that lateral overgrowth that could occur in formation of only Si epitaxial layer can be effectively restricted. By adjusting Ge density, SiGe migration is induced at selective epitaxial growth temperatures for forming the conventional Si epitaxial layer. And, by utilizing the internal stress of SiGe and lattice mismatch between the SiGe epitaxial layer and the Si epitaxial layer, the lateral overgrowth is restricted. Furthermore, by hydrogen thermal processing, surface topology of the epitaxial layer is improved.Type: ApplicationFiled: January 26, 2001Publication date: November 15, 2001Inventors: Seung-Ho Hahn, Dae-Hee Weon, Jeong-Youb Lee, Jung-Ho Lee, Chung-Tae Kim
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Publication number: 20010029092Abstract: A method for forming a gate structure begins by preparing a semiconductor substrate provided with an isolation region formed therein. A thin SiO2 layer is thermally grown on top of the semiconductor device by using a wet H2/O2 or a dry O2. And then, an aluminum oxide layer is formed on top of the semiconductor substrate with doping a dopant in situ. A conductive layer is formed on top of the Al2O3 layer. Finally, the conductive layer and the Al2O3 layer are patterned into the gate structure. The dopant is a material selected from a group consisting of Si, Zr, Hf, Nb or the like.Type: ApplicationFiled: December 4, 2000Publication date: October 11, 2001Inventors: Dae-Gyu Park, Se-Aug Jang, Jeong-Youb Lee, Hung-Jae Cho, Jung-Ho Kim
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Publication number: 20010024860Abstract: A method for forming a gate structure begins by preparing a semiconductor substrate provided with an isolation region formed therein. An aluminum oxide (Al2O3) layer is deposited on top of the semiconductor substrate and then, silicon ions plasma doping is carried out. Thereafter, the Al2O3 layer doped with silicon ions is annealed in the presence of oxygen gas or nitrous oxygen to remove a metallic vacancy in the Al2O3 layer. Subsequently, a conductive layer is formed on top of the Al2O3 layer. Finally, the conductive layer is patterned into the gate structure.Type: ApplicationFiled: December 19, 2000Publication date: September 27, 2001Inventors: Dae-Gyu Park, Se-Aug Jang, Jeong-Youb Lee