Patents by Inventor Jeong-Young Lee
Jeong-Young Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7320906Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode on the first portion of the lower conductive film; removing the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.Type: GrantFiled: August 19, 2004Date of Patent: January 22, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Min-Wook Park, Bum-Ki Baek, Jeong-Young Lee, Kwon-Young Choi, Sang-Ki Kwak, Sang-Jin Jeon
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Patent number: 7265799Abstract: A method of manufacturing a thin film transistor array panel is provided, the method includes: forming a gate line on an insulating substrate; forming a gate insulating layer; forming a semiconductor layer; forming a data conductive layer including a data line and a drain electrode; depositing a passivation layer; forming a photoresist including a first portion located on an end portion of the gate line, a second portion thicker than the first portion and located on the drain electrode, and a third portion thicker than the second portion; exposing a portion of the passivation layer under the second portion of the photoresist and a portion of the gate insulating layer under the first portion of the photoresist by etching using the photoresist as an etch mask; forming first and second contact holes exposing the drain electrode and the end portions of the gate line, respectively; and forming a pixel electrode connected to the drain electrode through the first contact hole.Type: GrantFiled: January 16, 2004Date of Patent: September 4, 2007Assignee: Samsung Electronics Co., LtdInventors: Jun-Hyung Souk, Jeong-Young Lee, Jong-Soo Yoon, Kwon-Young Choi, Bum-Ki Baek
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Publication number: 20070200981Abstract: A method of manufacturing a thin film transistor array panel is provided, the method includes: forming a gate line on an insulating substrate; forming a gate insulating layer; forming a semiconductor layer; forming a data conductive layer including a data line and a drain electrode; depositing a passivation layer; forming a photoresist including a first portion located on an end portion of the gate line, a second portion thicker than the first portion and located on the drain electrode, and a third portion thicker than the second portion; exposing a portion of the passivation layer under the second portion of the photoresist and a portion of the gate insulating layer under the first portion of the photoresist by etching using the photoresist as an etch mask; forming first and second contact holes exposing the drain electrode and the end portions of the gate line, respectively; and forming a pixel electrode connected to the drain electrode through the first contact hole.Type: ApplicationFiled: April 27, 2007Publication date: August 30, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jun-Hyung SOUK, Jeong-Young Lee, Jong-Soo Yoon, Kwon-Young Choi, Bum-Ki Baek
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Publication number: 20070190706Abstract: A method of manufacturing a thin film transistor array panel is provided, the method includes: forming a gate line on an insulating substrate; forming a gate insulating layer; forming a semiconductor layer; forming a data conductive layer including a data line and a drain electrode; depositing a passivation layer; forming a photoresist including a first portion located on an end portion of the gate line, a second portion thicker than the first portion and located on the drain electrode, and a third portion thicker than the second portion; exposing a portion of the passivation layer under the second portion of the photoresist and a portion of the gate insulating layer under the first portion of the photoresist by etching using the photoresist as an etch mask; forming first and second contact holes exposing the drain electrode and the end portions of the gate line, respectively; and forming a pixel electrode connected to the drain electrode through the first contact hole.Type: ApplicationFiled: March 23, 2007Publication date: August 16, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jun-Hyung Souk, Jeong-Young Lee, Jong-Soo Yoon, Kwon-Young Choi, Bum-Ki Baek
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Publication number: 20070177091Abstract: A liquid crystal display is provided, which includes: a first substrate; a first signal line formed on the first substrate; a second signal line formed on the first substrate and intersecting the first signal line; a thin film transistor connected to the first and the second signal lines; a pixel electrode connected to the thin film transistor; a second substrate; a common electrode formed on the second substrate; a liquid crystal layer interposed between the first substrate and the second substrate; and a tilt direction determining member formed on one of the first and the second substrates and having a notch.Type: ApplicationFiled: April 9, 2007Publication date: August 2, 2007Inventors: Jang-Kun Song, Sahng-Ik Jun, Jae-Hong Jeon, Jeong-Young Lee, Jae-Ho Lee
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Patent number: 7218369Abstract: A liquid crystal display is provided, which includes: a first substrate; a first signal line formed on the first substrate; a second signal line formed on the first substrate and intersecting the first signal line; a thin film transistor connected to the first and the second signal lines; a pixel electrode connected to the thin film transistor; a second substrate; a common electrode formed on the second substrate; a liquid crystal layer interposed between the first substrate and the second substrate; and a tilt direction determining member formed on one of the first and the second substrates and having a notch.Type: GrantFiled: October 15, 2004Date of Patent: May 15, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Jang-Kun Song, Sahng-Ik Jun, Jae-Hong Jeon, Jeong-Young Lee, Jae-Ho Lee
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Publication number: 20070091220Abstract: A thin film transistor array panel is provided, which includes: a substrate; a first signal line formed on the substrate; a second signal line formed on the substrate and intersecting the first signal line; a thin film transistor including a gate electrode connected to the first signal line and having an edge substantially parallel to the first signal line, a source electrode connected to the second signal line, and a drain electrode overlapping the edge of the gate electrode; and a pixel electrode connected to the drain electrode.Type: ApplicationFiled: December 18, 2006Publication date: April 26, 2007Inventors: Sahng-Ik Jun, Jae-Hong Jeon, Kwon-Young Choi, Jeong-Young Lee
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Publication number: 20060289965Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode and a pair of redundant electrodes on the first and the second portions of the lower conductive film, respectively, the redundant electrodes exposing a part of the second portion of the lower conductive film; removing the exposed part of the second portion of the lower conductive film to expose a portion of the semiconType: ApplicationFiled: August 30, 2006Publication date: December 28, 2006Inventors: Min-Wook Park, Sang-Jin Jeon, Jung-Joon Park, Jeong-Young Lee, Bum-Ki Baek, Se-Hwan Yu, Sang-Ki Kwak, Han-Ju Lee, Kwon-Young Choi
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Patent number: 7151279Abstract: A thin film transistor array panel is provided, which includes: a substrate; a first signal line formed on the substrate; a second signal line formed on the substrate and intersecting the first signal line; a thin film transistor including a gate electrode connected to the first signal line and having an edge substantially parallel to the first signal line, a source electrode connected to the second signal line, and a drain electrode overlapping the edge of the gate electrode; and a pixel electrode connected to the drain electrode.Type: GrantFiled: September 29, 2004Date of Patent: December 19, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Sahng-Ik Jun, Jae-Hong Jeon, Kwon-Young Choi, Jeong-Young Lee
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Patent number: 7119368Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode and a pair of redundant electrodes on the first and the second portions of the lower conductive film, respectively, the redundant electrodes exposing a part of the second portion of the lower conductive film; removing the exposed part of the second portion of the lower conductive film to expose a portion of the semiconType: GrantFiled: August 26, 2004Date of Patent: October 10, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Min-Wook Park, Sang-Jin Jeon, Jung-Joon Park, Jeong-Young Lee, Bum-Ki Baek, Se-Hwan Yu, Sang-Ki Kwak, Han-Ju Lee, Kwon-Young Choi
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Publication number: 20060172472Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode on the first portion of the lower conductive film; removing the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.Type: ApplicationFiled: March 30, 2006Publication date: August 3, 2006Inventors: Jeong-Young Lee, Se-Hwam Yu, Sang-Jin Jeon, Min-Wook Park
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Patent number: 7023016Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode on the first portion of the lower conductive film; removing the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.Type: GrantFiled: July 1, 2004Date of Patent: April 4, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Jeong-Young Lee, Se-Hwan Yu, Sang-Jin Jeon, Min-Wook Park
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Publication number: 20050162596Abstract: A liquid crystal display includes opening patterns in the electrodes or protrusions on the electrodes. The opening patterns or the protrusions have a pattern which controls the direction of the liquid crystal molecules. Thus the quality of the LCD can be improved.Type: ApplicationFiled: January 27, 2005Publication date: July 28, 2005Inventors: Hee-Joon Kim, Bum-Ki Baek, Jeong-Young Lee, Jae-Hong Jeon
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Publication number: 20050122459Abstract: A liquid crystal display is provided, which includes: a first substrate; a first signal line formed on the first substrate; a second signal line formed on the first substrate and intersecting the first signal line; a thin film transistor connected to the first and the second signal lines; a pixel electrode connected to the thin film transistor; a second substrate; a common electrode formed on the second substrate; a liquid crystal layer interposed between the first substrate and the second substrate; and a tilt direction determining member formed on one of the first and the second substrates and having a notch.Type: ApplicationFiled: October 15, 2004Publication date: June 9, 2005Inventors: Jang-Kun Song, Sahng-Ik Jun, Jae-Hong Jeon, Jeong-Young Lee, Jae-Ho Lee
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Publication number: 20050110014Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode on the first portion of the lower conductive film; removing the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.Type: ApplicationFiled: August 19, 2004Publication date: May 26, 2005Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Min-Wook Park, Bum-Ki Baek, Jeong-Young Lee, Kwon-Young Choi, Sang-Ki Kwak, Sang-Jin Jeon
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Publication number: 20050104069Abstract: A thin film transistor array panel is provided, which includes: a substrate; a first signal line formed on the substrate; a second signal line formed on the substrate and intersecting the first signal line; a thin film transistor including a gate electrode connected to the first signal line and having an edge substantially parallel to the first signal line, a source electrode connected to the second signal line, and a drain electrode overlapping the edge of the gate electrode; and a pixel electrode connected to the drain electrode.Type: ApplicationFiled: September 29, 2004Publication date: May 19, 2005Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sahng-Ik Jun, Jae-Hong Jeon, Kwon-Young Choi, Jeong-Young Lee
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Publication number: 20050082535Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode and a pair of redundant electrodes on the first and the second portions of the lower conductive film, respectively, the redundant electrodes exposing a part of the second portion of the lower conductive film; removing the exposed part of the second portion of the lower conductive film to expose a portion of the semiconType: ApplicationFiled: August 26, 2004Publication date: April 21, 2005Inventors: Min-Wook Park, Sang-Jin Jeon, Jung-Joon Park, Jeong-Young Lee, Bum-Ki Baek, Se-Hwan Yu, Sang-Ki Kwak, Han-Ju Lee, Kwon-Young Choi
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Publication number: 20050030440Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode on the first portion of the lower conductive film; removing the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.Type: ApplicationFiled: July 1, 2004Publication date: February 10, 2005Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jeong-Young Lee, Se-Hwan Yu, Sang-Jin Jeon, Min-Wook Park
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Publication number: 20040266039Abstract: To improve product yield, light is scanned on a layer on a substrate through a mask. A pattern is formed on the substrate by the exposure of the layer. The direction of scanning is substantially perpendicular to a longitudinal direction of the pattern. The capacitance difference due to coupling of the pattern to be formed and a conductive layer formed through an insulation layer is reduced. Thus, failures of a display device are reduced and the product yield is increased.Type: ApplicationFiled: April 1, 2004Publication date: December 30, 2004Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Soon-Il Ahn, Byoung-Sun Na, Jeong-Young Lee, You-Lee Song
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Patent number: 6798489Abstract: A liquid crystal display includes a bottom substrate with a gate wire, a data wire and thin transistor, and a top substrate with color filters. In a method for fabricating the liquid crystal display, a pixel electrode is formed on the bottom substrate at each pixel area using a first mask such that the pixel electrode has a first region with a smooth surface, and a second region with a rough surface. A common electrode is formed on the top substrate using a second mask such that the common electrode has a first region with a smooth surface, and a second region with a rough surface. The bottom substrate and the top substrate are assembled together, and a liquid crystal is injected between the bottom and the top substrates.Type: GrantFiled: November 4, 2003Date of Patent: September 28, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Jeong-Ho Lee, Young-Bae Park, Jeong-Young Lee