Abstract: A memory device includes memory banks that each include a bank array having memory cells, a row decoder, and a column decoder. Each memory cell includes a capacitor and a transistor, a write circuit to store input data received at the memory device from a test device in the bank array, a read circuit to generate output data based on reading data stored in the bank array, a parity data management circuit to generate first parity data smaller than the input data using the input data, generate second parity data smaller than the output data using the output data, and generate third parity data using the first and second parity data, and an output circuit to output at least one of the first, second, and third parity data as verification data, in response to receipt of a request from the test device at the memory device.

Abstract: A memory apparatus includes a memory cell array including a plurality of memory cells, a temperature sensor, a temperature compensated self refresh (TCSR) block, and a command controller. The temperature sensor is configured to generate temperature information by measuring internal temperature of the memory apparatus. The TCSR block is configured to vary and output, in a test mode of the memory apparatus, period information for adjusting a refresh period for the memory cell array according to the temperature information. The command controller is configured to adjust, in response to the period information, the refresh period for the memory cell array by controlling an external command.

Abstract: A memory device comprises a plurality of memory banks, each of the plurality of memory banks includes a bank array having a plurality of memory cells, a row decoder selecting at least one of word lines connecting to the plurality of memory cells, and a column decoder selecting at least one of bit lines connecting to the plurality of memory cells, and each of the plurality of memory cells includes a capacitor and a transistor, a write circuit configured to store input data received at the memory device from a test device in the bank array, a read circuit configured to generate output data based on reading data stored in the bank array, a parity data management circuit configured to generate first parity data having a size smaller than the input data using the input data, generate second parity data having a size smaller than the output data using the output data, and generate third parity data using the first parity data and the second parity data, and an output circuit configured to output at least one instan

Abstract: A memory apparatus includes a memory cell array including a plurality of memory cells, a temperature sensor, a temperature compensated self refresh (TCSR) block, and a command controller. The temperature sensor is configured to generate temperature information by measuring internal temperature of the memory apparatus. The TCSR block is configured to vary and output, in a test mode of the memory apparatus, period information for adjusting a refresh period for the memory cell array according to the temperature information. The command controller is configured to adjust, in response to the period information, the refresh period for the memory cell array by controlling an external command.

Abstract: A memory device includes memory cell array and an address decoder. The memory cell array includes a normal memory region and a redundant memory region. The normal memory region operates in response to data signal and plurality of normal memory region signals. The redundant memory region operates in response to data signal and plurality of redundant memory region signals. The address decoder includes normal memory region signal generator and redundant memory region signal generator. The normal memory region signal generator activates first normal memory region signals and redundant memory region signal generator activates first redundant memory region signal simultaneously when address decoder operates in test mode. First normal memory region signals correspond to an address signal and are included in plurality of normal memory region signals. A first redundant memory region signal corresponds to an address signal and is included in the plurality of redundant memory region signals.

Abstract: A memory device includes memory cell array and an address decoder. The memory cell array includes a normal memory region and a redundant memory region. The normal memory region operates in response to data signal and plurality of normal memory region signals. The redundant memory region operates in response to data signal and plurality of redundant memory region signals. The address decoder includes normal memory region signal generator and redundant memory region signal generator. The normal memory region signal generator activates first normal memory region signals and redundant memory region signal generator activates first redundant memory region signal simultaneously when address decoder operates in test mode. First normal memory region signals correspond to an address signal and are included in plurality of normal memory region signals. A first redundant memory region signal corresponds to an address signal and is included in the plurality of redundant memory region signals.

Abstract: A memory device includes a memory array, a plurality of input/output pins, a mask signal generator, an input/output block. The memory array is configured to output read data including a plurality of data bits. The mask signal generator is configured to generate at least one data mask signal. The input/output block is configured to mask bits having a logic level among the plurality of data bits in the read data to output the masked read data to the plurality of input/output pins.

Abstract: A memory device includes a memory array, a plurality of input/output pins, a mask signal generator, an input/output block. The memory array is configured to output read data including a plurality of data bits. The mask signal generator is configured to generate at least one data mask signal. The input/output block is configured to mask bits having a logic level among the plurality of data bits in the read data to output the masked read data to the plurality of input/output pins.