Abstract: Provided are a binder composition for a secondary battery electrode, and an electrode mixture including the same, and more particularly, a binder composition for a secondary battery electrode capable of providing excellent binding strength for an active material and an electrode while having excellent latex stability, thereby improving performance of a secondary battery, and an electrode mixture including the same.

Abstract: A light-emitting element transfer system includes raw film cutting device for forming a transfer member by cutting a raw film, a stretching device for stretching a transfer film with a plurality of light-emitting elements disposed thereon, a circuit board support member for supporting a circuit board and transport head for adsorbing the transfer member and transferring the light-emitting elements on the transfer film onto the circuit board by using the adsorbed transfer member.

Abstract: An apparatus for transferring light emitting elements includes: a transfer member including a stamp layer having an adhesive property and a base layer on a first surface of the stamp layer, the transfer member having a transfer portion, a folding portion, and an incision groove at a boundary between the transfer portion and the folding portion; a protective film on a second surface of the stamp layer, the protective film having an incision groove defining a transfer area and a folding area; an inversion member supporting the transfer member; and a transfer head including a chuck configured to adsorb to the base layer and to move the transfer member vertically and horizontally. The transfer portion is at a center with respect to the incision groove, and the folding portion is at an outer side of the incision groove with respect to the transfer portion.

Abstract: The present disclosure relates to an electrode binder composition for a rechargeable battery and an electrode mixture including the same. The electrode binder composition comprising an emulsified polymer particle having a core-shell structure can maintain a structural stability of the electrode even in repeated charge and discharge cycles, while having excellent properties in terms of a binding force, a mechanical property or the like, thereby improving the overall performance of the rechargeable battery.

Abstract: A quantum dot including a core that includes a first semiconductor nanocrystal including zinc and selenium, and optionally sulfur and/or tellurium, and a shell that includes a second semiconductor nanocrystal including zinc, and at least one of sulfur or selenium is disclosed. The quantum dot has an average particle diameter of greater than or equal to about 13 nm, an emission peak wavelength in a range of about 440 nm to about 470 nm, and a full width at half maximum (FWHM) of an emission wavelength of less than about 25 nm. A method for preparing the quantum dot, a quantum dot-polymer composite including the quantum dot, and an electronic device including the quantum dot is also disclosed.

Abstract: An apparatus for manufacturing an organic material includes an outer tube including an internal accommodating space, and at least one loading inner tube and at least one collecting inner tube disposed in the accommodation space, the loading inner tube including a mesh boat disposed in a first direction in which the loading inner tube extends.

Abstract: The present disclosure may provide a method of fabricating a display panel, the method includes picking up, by a transfer head, a transfer member located on a support member, detaching a light-emitting element from a donor substrate by attaching the transfer member picked up by the transfer head to the light-emitting element on the donor substrate to lift the light-emitting element, aligning, by the transfer head, the light-emitting element attached to the transfer member on a circuit board, and detaching the transfer member from the transfer head, bonding the light-emitting element attached to the transfer member onto the circuit board and separating, by the transfer head, the transfer member from the light-emitting element bonded to the circuit board to remove the transfer member.

Abstract: A polythiol composition according to exemplary embodiments includes: a polythiol-based compound; and a benzyl halide-based reaction regulator in an amount of 10 ppm to 2,000 ppm based on a weight of the polythiol-based compound. The reaction rate of the polythiol-based compound and an isocyanate-based compound may be controlled through the reaction regulator to inhibit a generation of stria phenomenon.

Abstract: Disclosed are a nonspecific immunostimulant composition, a preparation method thereof, and uses thereof. The composition includes 150 to 300 wt. parts of sodium silicate, 2˜8 wt. parts of sodium thiosulfate, 0.5˜2 wt. parts of sodium carbonate, 0.5˜2 wt. parts of potassium chloride, 200˜400 wt. parts of white sugar, and 300˜400 wt. parts of water, based on 100 wt. parts of potassium carbonate. The composition exhibits excellent defense against the mortality caused by AIV H5N1, thus improving the survival of infected animals. As a supplement of a formulated feed mixture for farmed aquatic organisms, the composition provides excellent immunostimulation and disease resistance so as to decrease the mass mortality of aquatic organisms and to increase productivity. Particularly, when raised with a food in mixture with the composition, livestock and farmed aquatic organisms are immunologically improved so that they can endure and are protected against epidemic diseases caused by viruses and bacteria.

Abstract: Disclosed are a nonspecific immunostimulant composition, a preparation method thereof, and uses thereof. The composition includes 150 to 300 wt. parts of sodium silicate, 2˜8 wt. parts of sodium thiosulfate, 0.5˜2 wt. parts of sodium carbonate, 0.5˜2 wt. parts of potassium chloride, 200˜400 wt. parts of white sugar, and 300˜400 wt. parts of water, based on 100 wt. parts of potassium carbonate. The composition exhibits excellent defense against the mortality caused by AIV H5N1, thus improving the survival of infected animals. As a supplement of a formulated feed mixture for farmed aquatic organisms, the composition provides excellent immunostimulation and disease resistance so as to decrease the mass mortality of aquatic organisms and to increase productivity. Particularly, when raised with a food in mixture with the composition, livestock and farmed aquatic organisms are immunologically improved so that they can endure and are protected against epidemic diseases caused by viruses and bacteria.

Abstract: An integrated circuit device includes a transistor array having a vertical stack of independently controllable gate electrodes therein. A first semiconductor channel region is provided, which extends on a first sidewall of the vertical stack of independently controllable gate electrodes. A first electrically insulating layer is also provided, which extends between the first semiconductor channel region and the first sidewall of the vertical stack of independently controllable gate electrodes. Source and drain regions are provided, which are electrically coupled to first and second ends of the first semiconductor channel region, respectively.

Abstract: A semiconductor device having reduced leakage current and increased capacitance without increasing an equivalent oxide thickness (EOT) can be manufactured by a method that includes providing a substrate having a dummy gate pattern; forming a gate forming trench by removing the dummy gate pattern; forming a stacked insulation layer within the gate forming trench, wherein the forming of the stacked insulation layer includes forming a first high-k dielectric layer, forming a second high-k dielectric layer by performing heat treatment on the first high-k dielectric layer, and, after the heat treatment, forming a third high-k dielectric layer on the second high-k dielectric layer, the third high-k dielectric layer having a higher relative permittivity than the second high-k dielectric layer and having a dielectric constant of 40 or higher; and forming a gate electrode within the gate forming trench.

Abstract: A method for manufacturing a semiconductor may include providing a substrate having first and second regions defined therein, forming an interlayer dielectric layer including first and second trenches formed in the first and second regions, respectively, and conformally forming a gate dielectric layer along a top surface of the interlayer dielectric layer, side and bottom surfaces of the first trench and side, and bottom surfaces of the second trench. An etch stop dielectric layer may be formed on the gate dielectric layer, a first metal layer may be formed to fill the first and second trenches, and the first metal layer in the first region may be removed using the etch stop dielectric layer as an etch stopper.

Abstract: A method for manufacturing a semiconductor may include providing a substrate having first and second regions defined therein, forming an interlayer dielectric layer including first and second trenches formed in the first and second regions, respectively, and conformally forming a gate dielectric layer along a top surface of the interlayer dielectric layer, side and bottom surfaces of the first trench and side, and bottom surfaces of the second trench. An etch stop dielectric layer may be formed on the gate dielectric layer, a first metal layer may be formed to fill the first and second trenches, and the first metal layer in the first region may be removed using the etch stop dielectric layer as an etch stopper.

Abstract: Provided is a semiconductor device that can include a lower interconnection on a substrate and at least one upper interconnection disposed on the lower interconnection. At least one gate structure can be disposed between the upper interconnection and the lower interconnection, where the gate structure can include a plurality of gate lines that are vertically stacked so that each of the gate lines has a wiring portion that is substantially parallel to an upper surface of the substrate and a contact portion that extends from the wiring portion along a direction penetrating an upper surface of the substrate. At least one semiconductor pattern can connect the upper and lower interconnections.

Abstract: An integrated circuit device includes a transistor array having a vertical stack of independently controllable gate electrodes therein. A first semiconductor channel region is provided, which extends on a first sidewall of the vertical stack of independently controllable gate electrodes. A first electrically insulating layer is also provided, which extends between the first semiconductor channel region and the first sidewall of the vertical stack of independently controllable gate electrodes. Source and drain regions are provided, which are electrically coupled to first and second ends of the first semiconductor channel region, respectively.

Abstract: A method of fabricating a semiconductor device may include: preparing a substrate in which first and second regions are defined; forming an interlayer insulating film, which includes first and second trenches, on the substrate; forming a work function control film, which contains Al and N, along a top surface of the interlayer insulating film, side and bottom surfaces of the first trench, and side and bottom surfaces of the second trench; forming a mask pattern on the work function control film formed in the second region; injecting a work function control material into the work function control film formed in the first region to control a work function of the work function control film formed in the first region; removing the mask pattern; and forming a first metal gate electrode to fill the first trench and forming a second metal gate electrode to fill the second trench.

Abstract: An integrated circuit device includes a transistor array having a vertical stack of independently controllable gate electrodes therein. A first semiconductor channel region is provided, which extends on a first sidewall of the vertical stack of independently controllable gate electrodes. A first electrically insulating layer is also provided, which extends between the first semiconductor channel region and the first sidewall of the vertical stack of independently controllable gate electrodes. Source and drain regions are provided, which are electrically coupled to first and second ends of the first semiconductor channel region, respectively.

Abstract: A method for manufacturing a semiconductor may include providing a substrate having first and second regions defined therein, forming an interlayer dielectric layer including first and second trenches formed in the first and second regions, respectively, and conformally forming a gate dielectric layer along a top surface of the interlayer dielectric layer, side and bottom surfaces of the first trench and side, and bottom surfaces of the second trench. An etch stop dielectric layer may be formed on the gate dielectric layer, a first metal layer may be formed to fill the first and second trenches, and the first metal layer in the first region may be removed using the etch stop dielectric layer as an etch stopper.

Abstract: A semiconductor device having reduced leakage current and increased capacitance without increasing an equivalent oxide thickness (EOT) can be manufactured by a method that includes providing a substrate having a dummy gate pattern; forming a gate forming trench by removing the dummy gate pattern; forming a stacked insulation layer within the gate forming trench, wherein the forming of the stacked insulation layer includes forming a first high-k dielectric layer, forming a second high-k dielectric layer by performing heat treatment on the first high-k dielectric layer, and, after the heat treatment, forming a third high-k dielectric layer on the second high-k dielectric layer, the third high-k dielectric layer having a higher relative permittivity than the second high-k dielectric layer and having a dielectric constant of 40 or higher; and forming a gate electrode within the gate forming trench.