Patents by Inventor Jeonghee Shin

Jeonghee Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12093541
    Abstract: Techniques are disclosed relating to bandwidth compensation for certain memory traffic at high temperatures. In some embodiments, processor circuitry is configured to execute memory access operations for multiple traffic classes, including a first traffic class (e.g., real-time traffic) associated with a bandwidth quality-of-service parameter and a second traffic class (e.g., low-latency traffic). In some embodiments, memory controller circuitry is configured to access storage circuitry to perform the memory access operations, determine a temperature value associated with the storage circuitry, and, based on detection of a first temperature scenario for the storage circuitry, allocate memory access operations among the first and second traffic class according to a first allocation policy.
    Type: Grant
    Filed: September 6, 2022
    Date of Patent: September 17, 2024
    Assignee: Apple Inc.
    Inventors: Gregory S. Mathews, Jeonghee Shin
  • Patent number: 12079144
    Abstract: An apparatus includes a communication bus circuit, a memory circuit, a queue manager circuit, and an arbitration circuit. The communication bus circuit includes a command bus and a data bus separate from the command bus. The queue manager circuit may be configured to receive a first memory request and a second memory request, each request including a respective address value to be sent via the command bus. The first memory request may include a corresponding data operand to be sent via the data bus. The queue manager circuit may also be configured to distribute the first memory request and the second memory request among a plurality of bus queues. Distribution of the first and second memory requests may be based on the respective address values. The arbitration circuit may be configured to select a particular memory request from a particular one of the plurality of bus queues.
    Type: Grant
    Filed: November 10, 2022
    Date of Patent: September 3, 2024
    Assignee: Apple Inc.
    Inventors: Sebastian Werner, Amir Kleen, Jeonghee Shin, Peter A. Lisherness
  • Patent number: 12039169
    Abstract: A memory controller may include a dynamic arbitration scheme to dynamically vary arbitration factors of two or more traffic classes based on dynamic latency tolerance, requested and available bandwidths on an interconnect from source agents to memory controllers, and other dynamic and static factors.
    Type: Grant
    Filed: August 31, 2022
    Date of Patent: July 16, 2024
    Assignee: Apple Inc.
    Inventors: Anjana Subramanian, Rohit Natarajan, Yu Simon Zhang, Mukul A. Joshi, Harshavardhan Kaushikkar, Jeonghee Shin, Srinivasa Rangan Sridharan
  • Patent number: 11824795
    Abstract: Techniques are disclosed relating to merging virtual communication channels in a portion of a computing system. In some embodiments, a communication fabric routes first and second classes of traffic with different quality-of-service parameters, using a first virtual channel for the first class and a second virtual channel for the second class. In some embodiments, a memory controller communicates, via the fabric, using a merged virtual channel configured to handle traffic from both the first virtual channel and the second virtual channel. In some embodiments, the system limits the rate at which an agent is allowed to transmit requests of the second class of traffic, but requests by the agent for the first class of traffic are not rate limited. Disclosed techniques may improve independence of virtual channels, relative to sharing the same channel in an entire system, without unduly increasing complexity.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: November 21, 2023
    Inventors: Rohit K. Gupta, Gregory S. Mathews, Harshavardhan Kaushikkar, Jeonghee Shin, Rohit Natarajan
  • Publication number: 20230325086
    Abstract: A memory controller may include a dynamic arbitration scheme to dynamically vary arbitration factors of two or more traffic classes based on dynamic latency tolerance, requested and available bandwidths on an interconnect from source agents to memory controllers, and other dynamic and static factors.
    Type: Application
    Filed: August 31, 2022
    Publication date: October 12, 2023
    Inventors: Anjana Subramanian, Rohit Natarajan, Yu Simon Zhang, Mukul A. Joshi, Harshavardhan Kaushikkar, Jeonghee Shin, Srinivasa Rangan Sridharan
  • Publication number: 20230064187
    Abstract: Techniques are disclosed relating to merging virtual communication channels in a portion of a computing system. In some embodiments, a communication fabric routes first and second classes of traffic with different quality-of-service parameters, using a first virtual channel for the first class and a second virtual channel for the second class. In some embodiments, a memory controller communicates, via the fabric, using a merged virtual channel configured to handle traffic from both the first virtual channel and the second virtual channel. In some embodiments, the system limits the rate at which an agent is allowed to transmit requests of the second class of traffic, but requests by the agent for the first class of traffic are not rate limited. Disclosed techniques may improve independence of virtual channels, relative to sharing the same channel in an entire system, without unduly increasing complexity.
    Type: Application
    Filed: November 17, 2021
    Publication date: March 2, 2023
    Inventors: Rohit K. Gupta, Gregory S. Mathews, Harshavardhan Kaushikkar, Jeonghee Shin, Rohit Natarajan
  • Patent number: 10545739
    Abstract: A low level virtual machine (LLVM)-based system C compiler for architecture synthesis is provided. In one aspect, a method for translating a system C model to hardware description language (HDL) is provided. The method includes the steps of: generating a hardware connection model (HCM) from the system C model, wherein the HCM defines modules and interconnects in a hardware system; parsing the system C model into a LLVM intermediate representation (IR); converting the LLVM IR to a system LLVM IR which records correspondence information between the LLVM IR and the HCM; and generating the HDL based on direct mapping of processes from the system LLVM IR and the HCM.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: January 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Minsik Cho, Brian R. Konigsburg, Indira Nair, Haoxing Ren, Jeonghee Shin
  • Patent number: 9858373
    Abstract: A graph is constructed, having a plurality of nodes representing a plurality of logical operations and a plurality of edges connecting those of the plurality of nodes which do not conflict. A weight, including a width difference between end nodes of each of the edges, is assigned to each edge. Weighted cliques are enumerated, each including at least two of the nodes. Each of the weighted cliques is replaced with a single one of the logical operations and a multiplexer, to obtain a plurality of multiplexer-operation groups, such that each logical operation in one of the multiplexer-operation groups can be shared within a same clock cycle of a digital electronic integrated circuit.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: January 2, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Minsik Cho, Brian R. Konigsburg, Jeonghee Shin
  • Publication number: 20170286079
    Abstract: A low level virtual machine (LLVM)-based system C compiler for architecture synthesis is provided. In one aspect, a method for translating a system C model to hardware description language (HDL) is provided. The method includes the steps of: generating a hardware connection model (HCM) from the system C model, wherein the HCM defines modules and interconnects in a hardware system; parsing the system C model into a LLVM intermediate representation (IR); converting the LLVM IR to a system LLVM IR which records correspondence information between the LLVM IR and the HCM; and generating the HDL based on direct mapping of processes from the system LLVM IR and the HCM.
    Type: Application
    Filed: April 5, 2016
    Publication date: October 5, 2017
    Inventors: Minsik Cho, Brian R. Konigsburg, Indira Nair, Haoxing Ren, Jeonghee Shin
  • Patent number: 9665674
    Abstract: In a computing system running an environment for designing operation of circuitry, at least the following are performed for providing simulations and evaluations of one or more user-defined modules of circuitry including one or more pipeline stages in a pipeline. A model of the pipeline is automatically generated by using a pipeline block diagram, where the model is generated in a high-level modeling language able to perform simulations of circuitry with the pipeline. An interface is automatically generated between the one or more user-defined modules and the generated model of the pipeline, the interface including access to the pipeline, wherein the pipeline access allows the one or more user-defined modules to interact indirectly. Evaluation is performed of the one or more user-defined modules using the automatically generated model of the pipeline and the automatically generated interface. Methods, apparatus, and computer program products are disclosed.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: May 30, 2017
    Assignee: International Business Machines Corporation
    Inventors: Minsik Cho, Brian R. Konigsburg, Indira Nair, Haoxing Ren, Jeonghee Shin
  • Publication number: 20170017747
    Abstract: A graph is constructed, having a plurality of nodes representing a plurality of logical operations and a plurality of edges connecting those of the plurality of nodes which do not conflict. A weight, including a width difference between end nodes of each of the edges, is assigned to each edge. Weighted cliques are enumerated, each including at least two of the nodes. Each of the weighted cliques is replaced with a single one of the logical operations and a multiplexer, to obtain a plurality of multiplexer-operation groups, such that each logical operation in one of the multiplexer-operation groups can be shared within a same clock cycle of a digital electronic integrated circuit.
    Type: Application
    Filed: July 15, 2015
    Publication date: January 19, 2017
    Inventors: Minsik Cho, Brian R. Konigsburg, Jeonghee Shin
  • Publication number: 20160350464
    Abstract: In a computing system running an environment for designing operation of circuitry, at least the following are performed for providing simulations and evaluations of one or more user-defined modules of circuitry including one or more pipeline stages in a pipeline. A model of the pipeline is automatically generated by using a pipeline block diagram, where the model is generated in a high-level modeling language able to perform simulations of circuitry with the pipeline. An interface is automatically generated between the one or more user-defined modules and the generated model of the pipeline, the interface including access to the pipeline, wherein the pipeline access allows the one or more user-defined modules to interact indirectly. Evaluation is performed of the one or more user-defined modules using the automatically generated model of the pipeline and the automatically generated interface. Methods, apparatus, and computer program products are disclosed.
    Type: Application
    Filed: May 24, 2016
    Publication date: December 1, 2016
    Inventors: Minsik Cho, Brian R. Konigsburg, Indira Nair, Haoxing Ren, Jeonghee Shin
  • Patent number: 9507891
    Abstract: In a computing system running an environment for designing operation of circuity, at least the following are performed for providing simulations and evaluations of one or more user-defined modules of circuitry including one or more pipeline stages in a pipeline. A model of the pipeline is automatically generated by using a pipeline block diagram, where the model is generated in a high-level modeling language able to perform simulations of circuitry with the pipeline. An interface is automatically generated between the one or more user-defined modules and the generated model of the pipeline, the interface including a set of access methods to the pipeline. Evaluation is performed of the one or more user-defined modules using the automatically generated model of the pipeline and the automatically generated interface. Methods, apparatus, and computer program products are disclosed.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: November 29, 2016
    Assignee: International Business Machines Corporation
    Inventors: Minsik Cho, Brian R. Konigsburg, Indira Nair, Haoxing Ren, Jeonghee Shin
  • Patent number: 9477797
    Abstract: In a computing system running an environment for designing operation of circuity, at least the following are performed for providing simulations and evaluations of one or more user-defined modules of circuitry including one or more pipeline stages in a pipeline. A model of the pipeline is automatically generated by using a pipeline block diagram, where the model is generated in a high-level modeling language able to perform simulations of circuitry with the pipeline. An interface is automatically generated between the one or more user-defined modules and the generated model of the pipeline, the interface including a set of access methods to the pipeline. Evaluation is performed of the one or more user-defined modules using the automatically generated model of the pipeline and the automatically generated interface. Methods, apparatus, and computer program products are disclosed.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: October 25, 2016
    Assignee: International Business Machines Corporation
    Inventors: Minsik Cho, Brian R. Konigsburg, Indira Nair, Haoxing Ren, Jeonghee Shin
  • Patent number: 9477568
    Abstract: A mechanism is provided for determining a modeled age of a set of interconnect groups in a set of cores in a set of multi-core processors. For each interconnect group in the set of interconnect groups in the set of cores on the set of multi-core processors, a determination is made of a current modeled age of the interconnect group. A determination is then made as to whether at least one current modeled age of the interconnect group for the set of interconnect groups is greater than an end-of-life value. Responsive to at least one current modeled age of the interconnect group being greater than the end-of-life value, an indication to take corrective action with the at least one associated interconnect group is sent.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: October 25, 2016
    Assignee: International Business Machines Corporation
    Inventors: Malcolm S. Allen-Ware, Jon A. Casey, Sungjun Chun, Alan J. Drake, Charles R. Lefurgy, Karthick Rajamani, Jeonghee Shin, Thomas A. Wassick, Victor Zyuban
  • Patent number: 9405866
    Abstract: In a computing system running an environment for designing operation of circuitry, at least the following are performed for providing simulations and evaluations of one or more user-defined modules of circuitry including one or more pipeline stages in a pipeline. A model of the pipeline is automatically generated by using a pipeline block diagram, where the model is generated in a high-level modeling language able to perform simulations of circuitry with the pipeline. An interface is automatically generated between the one or more user-defined modules and the generated model of the pipeline, the interface including a set of access methods to the pipeline. Evaluation is performed of the one or more user-defined modules using the automatically generated model of the pipeline and the automatically generated interface. Methods, apparatus, and computer program products are disclosed.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: August 2, 2016
    Assignee: International Business Machines Corporation
    Inventors: Minsik Cho, Brian R. Konigsburg, Indira Nair, Haoxing Ren, Jeonghee Shin
  • Publication number: 20150094995
    Abstract: A mechanism is provided for determining a modeled age of a set of interconnect groups in a set of cores in a set of multi-core processors. For each interconnect group in the set of interconnect groups in the set of cores on the set of multi-core processors, a determination is made of a current modeled age of the interconnect group. A determination is then made as to whether at least one current modeled age of the interconnect group for the set of interconnect groups is greater than an end-of-life value. Responsive to at least one current modeled age of the interconnect group being greater than the end-of-life value, an indication to take corrective action with the at least one associated interconnect group is sent.
    Type: Application
    Filed: September 27, 2013
    Publication date: April 2, 2015
    Applicant: International Business Machines Corporation
    Inventors: Malcolm S. Allen-Ware, Jon A. Casey, Sungjun Chun, Alan J. Drake, Charles R. Lefurgy, Karthick Rajamani, Jeonghee Shin, Thomas A. Wassick, Victor Zyuban
  • Patent number: 8914764
    Abstract: A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: December 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Pradip Bose, Alper Buyuktosunoglu, John A. Darringer, Moinuddin K. Qureshi, Jeonghee Shin
  • Patent number: 8863068
    Abstract: A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: October 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: Pradip Bose, Alper Buyuktosunoglu, John A. Darringer, Moinuddin K. Qureshi, Jeonghee Shin
  • Patent number: 8826203
    Abstract: A system and method for improving and optimizing current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The system and method enables rapid C4 bump current estimation and placement including generating a one-time computed sensitivity matrix that includes all of the contributions of macros (or groups of components) to C4 current. The system and method further enables the calculation of a C4 current changes using the one-time computed sensitivity matrix and redistributed currents due to deletion of one or more C4 connectors. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: September 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: John Darringer, Jeonghee Shin