Patents by Inventor Jeong-Ho Bang
Jeong-Ho Bang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12260930Abstract: A memory core characteristic screening method includes the following steps. A command signal transmitting step includes configuring a processing module to transmit a command signal to a memory device. A first internal operating step includes configuring the memory device to operate a first operation to one of a word line, a bit line pair and a column line after a first strobe signal delay time according to a first command. A second internal operating step includes configuring the memory device to operate a second operation to another one of the word line, the bit line pair and the column line after a second strobe signal delay time according to a second command. A memory core characteristic screening step includes screening a memory core characteristic by shorting a timing between the first strobe signal delay time and the second strobe signal delay time.Type: GrantFiled: December 23, 2022Date of Patent: March 25, 2025Assignee: INTEGRATED SILICON SOLUTION INC.Inventors: Jeong Ho Bang, Hyeon Jae Lee, Wol Jin Lee, Ki Hyung Ryoo, Kwang Rae Cho, Sun Byeong Yoon
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Patent number: 12183411Abstract: A memory interface circuitry includes a clock generator to convert the first clock signal into a second clock signal, a state machine to generate a test signal according to the second clock signal, a data pattern generator to generate a plurality of pre-defined data, a read register to sequentially output the plurality of pre-defined data, an I/O interface to capture a plurality of data from the plurality of pre-defined data according to a write strobe signal, a write register to receive and store the plurality of data from the I/O interface, and a comparator to compare the plurality of pre-defined data with the plurality of data to generate a test result. The test result is configured to verify an operation of the I/O interface.Type: GrantFiled: February 14, 2023Date of Patent: December 31, 2024Assignee: INTEGRATED SILICON SOLUTION INC.Inventors: Hyeon Jae Lee, Jeong Ho Bang, Wol Jin Lee, Ki Hyung Ryoo, Kwang Rae Cho, Sun Byeong Yoon
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Publication number: 20240274214Abstract: A memory interface circuitry includes a clock generator to convert the first clock signal into a second clock signal, a state machine to generate a test signal according to the second clock signal, a data pattern generator to generate a plurality of pre-defined data, a read register to sequentially output the plurality of pre-defined data, an I/O interface to capture a plurality of data from the plurality of pre-defined data according to a write strobe signal, a write register to receive and store the plurality of data from the I/O interface, and a comparator to compare the plurality of pre-defined data with the plurality of data to generate a test result. The test result is configured to verify an operation of the I/O interface.Type: ApplicationFiled: February 14, 2023Publication date: August 15, 2024Inventors: Hyeon Jae LEE, Jeong Ho BANG, Wol Jin LEE, Ki Hyung RYOO, Kwang Rae CHO, Sun Byeong YOON
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Publication number: 20240212728Abstract: A memory core characteristic screening method includes the following steps. A command signal transmitting step includes configuring a processing module to transmit a command signal to a memory device. A first internal operating step includes configuring the memory device to operate a first operation to one of a word line, a bit line pair and a column line after a first strobe signal delay time according to a first command. A second internal operating step includes configuring the memory device to operate a second operation to another one of the word line, the bit line pair and the column line after a second strobe signal delay time according to a second command. A memory core characteristic screening step includes screening a memory core characteristic by shorting a timing between the first strobe signal delay time and the second strobe signal delay time.Type: ApplicationFiled: December 23, 2022Publication date: June 27, 2024Inventors: Jeong Ho BANG, Hyeon Jae LEE, Wol Jin LEE, Ki Hyung RYOO, Kwang Rae CHO, Sun Byeong YOON
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Publication number: 20230252333Abstract: An apparatus for processing a photonic qubit signal includes a first optical unit to receive and transmit a time-modulated signal divided into two sections distinguished with respect to time and correspond to |0 and |1 states of single-photon qubit information; a second optical unit to form a first path-signal pattern by distributing the time-modulated signal into two spatial paths; a third optical unit to form a second path-signal pattern from the first path-signal pattern by inducing a relative delay and controlling a phase difference between signals on the two spatial paths; a fourth optical unit to form a third path-signal pattern through optical interference of the second path-signal pattern; and a fifth optical unit to control a phase difference between signals on the two spatial paths and form a fourth path-signal pattern through optical interference of the third path-signal pattern.Type: ApplicationFiled: February 2, 2023Publication date: August 10, 2023Inventors: Min Su KIM, In Gyoo KIM, Ki Won MOON, Jeong Ho BANG, Kyung Hyun BAEK, Jung Jin JU
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Patent number: 9426890Abstract: Disclosed herein is a display apparatus that reduces a magnitude of a tension applied to a flexible PCB when a display panel is provided with a curved surface, and prevents damage of a driving chip. The display apparatus in accordance with exemplary embodiments includes a display panel configured to display an image, a source printed circuit board configured to control the display panel, and a flexible PCB that connects the display panel and the source printed circuit board. A length of at least one side edge of the flexible PCB is formed longer than a minimum length from the display panel to the source printed circuit board.Type: GrantFiled: September 2, 2014Date of Patent: August 23, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyo Jae Jang, Chan Hong Park, Jeong Ho Bang, Jong Myung Lee, Sun Weon Jeong, Hyeong Sik Choi
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Publication number: 20150245488Abstract: Disclosed herein is a display apparatus that reduces a magnitude of a tension applied to a flexible PCB when a display panel is provided with a curved surface, and prevents damage of a driving chip. The display apparatus in accordance with exemplary embodiments includes a display panel configured to display an image, a source printed circuit board configured to control the display panel, and a flexible PCB that connects the display panel and the source printed circuit board. A length of at least one side edge of the flexible PCB is formed longer than a minimum length from the display panel to the source printed circuit board.Type: ApplicationFiled: September 2, 2014Publication date: August 27, 2015Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyo Jae JANG, Chan Hong PARK, Jeong Ho BANG, Jong Myung LEE, Sun Weon JEONG, Hyeong Sik CHOI
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Publication number: 20150212378Abstract: A display device and manufacturing method thereof. The display device includes a first substrate and a second substrate formed to face each other; a liquid crystal layer between the first and second substrates; a plurality of gate wirings and data wirings intersecting each other to form a plurality of pixel regions on the second substrate; and a first ground wiring formed on the first substrate configured to block a surge voltage from being applied to the pixel regions.Type: ApplicationFiled: January 27, 2015Publication date: July 30, 2015Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eui-Dong HWANG, Jeong Ho BANG, Yong Hwan PARK
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Patent number: 8018899Abstract: A handoff system and method between different kinds of devices, an SIP server and an application method of the SIP server applied thereto. The handoff system between different kinds of devices includes a plurality of devices; a SIP server which requests a routing path update when a handoff request signal is input from a source device among the plurality devices, and getting a target device to participate in a current session; and a gateway which updates a predetermined routing path when a request signal for the routing path update is input, and transmitting data to the source device and the target device via the updated routing path.Type: GrantFiled: February 16, 2006Date of Patent: September 13, 2011Assignees: Samsung Electronics Co., Ltd., Korea Advanced Institute of Science and Technology (KAIST)Inventors: Se-jong Oh, Jeong-ho Bang, Myung-cul Kim, Kyoung-hee Lee
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Patent number: 7602172Abstract: A test apparatus includes one handler connected to a tester and one test board divided into two or more sites or two or more test boards. Since only the sites on the test board (or test boards) need be duplicated, rather than the loading lanes or sorters of the handler, the test apparatus can be conveniently compact. Further, while testing semiconductor devices on one site or one test board, semiconductor devices in another site or on another test board can be sorted according to the test result. This enables the reduction or elimination of tester idle time to optimize the efficiency of the test apparatus.Type: GrantFiled: April 24, 2008Date of Patent: October 13, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Ae-Yong Chung, Sung-Ok Kim, Kyeong-Seon Shin, Jeong-Ho Bang
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Patent number: 7492032Abstract: A device and method of manufacturing a fuse region are disclosed. The fuse region may include an interlayer insulating layer formed on a substrate, a plurality of fuses disposed on the interlayer insulating layer, and fuse isolation walls located between the fuses, wherein each of the fuse isolation walls may include lower and upper fuse isolation patterns.Type: GrantFiled: April 19, 2005Date of Patent: February 17, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Kwang-Kyu Bang, Kun-Gu Lee, Kyoung-Suk Lyu, Jeong-Ho Bang, Kyeong-Seon Shin, Ho-Jeong Choi, Seung-Gyoo Choi
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Patent number: 7438563Abstract: In one embodiment, a connector is made using a mixture of insulating silicone powder and conductive powder. The connector comprises a connector body formed from the insulating silicone powder and on or more preferably regularly arrayed conductive silicone members that are formed by migrating the conductive powder to a site of the connector corresponding to a solder ball of the semiconductor package. The conductive silicone member comprises a high-density conductive silicone part formed to be proximate an upper surface of the connector body and to protrude therefrom and a low-density conductive silicone part formed in substantial vertical alignment beneath the high-density conductive silicone part, the low-density conductive silicone part having a lower surface exposed from a lower surface of the connector body.Type: GrantFiled: December 5, 2005Date of Patent: October 21, 2008Assignees: Samsung Electronics Co., Ltd., ISC Technology Co., Ltd.Inventors: Young-Bae Chung, Hyun-Seop Shim, Jeong-Ho Bang, Jae-Il Lee, Hyun-Kyo Seo, Young-Soo An, Soon-Geol Hwang
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Publication number: 20080197874Abstract: A test apparatus includes one handler connected to a tester and one test board divided into two or more sites or two or more test boards. Since only the sites on the test board (or test boards) need be duplicated, rather than the loading lanes or sorters of the handler, the test apparatus can be conveniently compact. Further, while testing semiconductor devices on one site or one test board, semiconductor devices in another site or on another test board can be sorted according to the test result. This enables the reduction or elimination of tester idle time to optimize the efficiency of the test apparatus.Type: ApplicationFiled: April 24, 2008Publication date: August 21, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ae-Yong CHUNG, Sung-Ok KIM, Kyeong-Seon SHIN, Jeong-Ho BANG
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Test system of semiconductor device having a handler remote control and method of operating the same
Patent number: 7408339Abstract: A test system of a semiconductor device for a handler remote control is provided. The system includes: a tester for testing the semiconductor device; a handler connected to the tester through a GPIB (General Purpose Instruction Bus) communication cable; a tester server connected to the tester to download a test program, handler remote control program and a handler state check program to the tester; and communication data transmitted and received through the GPIB communication cable between the tester and the handler, wherein the communication data has basic communication data for an electrical test of the semiconductor device, communication data for the handler remote control, and communication data for a handler state check.Type: GrantFiled: May 15, 2007Date of Patent: August 5, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Ae-Yong Chung, Eun-Seok Lee, Jeong-Ho Bang, Kyeong-Seon Shin, Dae-Gab Chi, Sung-Ok Kim -
Patent number: 7378864Abstract: A test apparatus includes one handler connected to a tester and one test board divided into two or more sites or two or more test boards. Since only the sites on the test board (or test boards) need be duplicated, rather than the loading lanes or sorters of the handler, the test apparatus can be conveniently compact. Further, while testing semiconductor devices on one site or one test board, semiconductor devices in another site or on another test board can be sorted according to the test result. This enables the reduction or elimination of tester idle time to optimize the efficiency of the test apparatus.Type: GrantFiled: March 28, 2005Date of Patent: May 27, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Ae-Yong Chung, Sung-Ok Kim, Kyeong-Seon Shin, Jeong-Ho Bang
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Patent number: 7327154Abstract: A test apparatus for testing a multi-chip package comprising a multiplicity of semiconductor chips, which includes a test driver having one drive channel and at least one input/output channel. A test board is mounted with the multi-chip package. Drive pins of the semiconductor chips are parallel connected to the drive channel, and input/output pins of the semiconductor chips are parallel connected to the input/output channel.Type: GrantFiled: July 27, 2005Date of Patent: February 5, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Gu Shin, Kyoung-Il Heo, Hyoung-Young Lee, Hyuk Kwon, Ki-Bong Ju, Jeong-Ho Bang, Hyun-Seop Shim
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TEST SYSTEM OF SEMICONDUCTOR DEVICE HAVING A HANDLER REMOTE CONTROL AND METHOD OF OPERATING THE SAME
Publication number: 20070290707Abstract: A test system of a semiconductor device for a handler remote control is provided. The system includes: a tester for testing the semiconductor device; a handler connected to the tester through a GPIB (General Purpose Instruction Bus) communication cable; a tester server connected to the tester to download a test program, handler remote control program and a handler state check program to the tester; and communication data transmitted and received through the GPIB communication cable between the tester and the handler, wherein the communication data has basic communication data for an electrical test of the semiconductor device, communication data for the handler remote control, and communication data for a handler state check.Type: ApplicationFiled: May 15, 2007Publication date: December 20, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ae-Yong CHUNG, Eun-Seok LEE, Jeong-Ho BANG, Kyeong-Seon SHIN, Dae-Gab CHI, Sung-Ok KIM -
Patent number: 7254757Abstract: A flash memory test system capable of test time reduction and an electrical test method using the same: The invention provides a parallel tester that includes a first memory and a second memory. The first and second memories are used to each supply different data to identical addresses within a plurality of DUTs, thereby making it possible to conduct in parallel tests such as trim tests, repair tests, and invalid block masking test. Thus parallel testing is done to replace testing that was previously done serially.Type: GrantFiled: September 29, 2004Date of Patent: August 7, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Kyoo Park, Jong-Kook Kim, Jeong-Ho Bang, Sang-Young Choi, Eun-Sik Kim
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Test system of semiconductor device having a handler remote control and method of operating the same
Patent number: 7230417Abstract: A test system of a semiconductor device for a handler remote control is provided. The system includes: a tester for testing the semiconductor device; a handler connected to the tester through a GPIB (General Purpose Instruction Bus) communication cable; a tester server connected to the tester to download a test program, handler remote control program and a handler state check program to the tester; and communication data transmitted and received through the GPIB communication cable between the tester and the handler, wherein the communication data has basic communication data for an electrical test of the semiconductor device, communication data for the handler remote control, and communication data for a handler state check.Type: GrantFiled: October 17, 2005Date of Patent: June 12, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Ae-Yong Chung, Eun-Seok Lee, Jeong-Ho Bang, Kyeong-Seon Shin, Dae-Gab Chi, Sung-Ok Kim -
Patent number: 7227351Abstract: Embodiments of the invention connect a plurality of devices under test (DUTS) in a parallel manner and a high test current is selectively applied to each DUT. The apparatus to test a plurality of DUTs includes a plurality of power sources providing the test current to a plurality of DUTs; and switching devices connected to the respective DUTs and power sources and selectively providing the test current. In addition, the apparatus has at least one control unit to control the switching devices. Furthermore, a group of DUTs from the plurality of DUTs is connected between two of the plurality of power sources in a parallel manner, and the test current is selectively provided to one DUT from the group of DUTs according to the operation of the switching devices.Type: GrantFiled: May 27, 2004Date of Patent: June 5, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Woo-Il Kim, Hyun-Seop Shim, Hyoung-Young Lee, Young-Ki Kwak, Jeong-Ho Bang, Ki-Bong Ju