Abstract: A compute express link (CXL) memory device includes a memory device storing data, and a controller configured to read the data from the memory device based on a first command received through a first protocol, select a calculation engine based on a second command received through a second protocol different from the first protocol, and control the calculation engine to perform a calculation on the read data.

Abstract: An integrated circuit device includes a pair of fin-type active regions collinear with each other on a substrate, a gate line disposed on one of the fin-type active regions, a capping insulating layer that covers the gate line, and a fin isolation insulating portion that passes through the capping insulating layer in a vertical direction between the pair of fin-type active regions. The fin isolation insulating portion includes an isolation insulating plug that includes a first portion disposed between the pair of fin-type active regions and a second portion integrally connected to the first portion and that passes through the capping insulating layer in the vertical direction, and an isolation insulating liner that surrounds a bottom surface and a sidewall of the isolation insulating plug. The isolation insulating liner includes an uppermost portion that is closer to the substrate than a top surface of the isolation insulating plug.

Abstract: Provided is an integrated circuit device including a plurality of fin-type active areas each extending on a substrate in a first horizontal direction, a plurality of gate structures each extending in a second horizontal direction intersecting the plurality of fin-type active areas on the substrate and spaced apart from each other in the first horizontal direction, an interlayer insulating layer covering the periphery of the plurality of gate structures, and an inter-gate cutting layer formed of an insulating material and extending in the first horizontal direction across through the plurality of gate structures and the interlayer insulating layer. A first gate structure is separated from a second gate structure by the inter-gate cutting layer, and portions of respective side surfaces of the gate structures overlap the plurality of fin-type active areas in a vertical direction, the respective side surfaces of the gate structures extending in the first horizontal direction.

Abstract: A memory module includes a memory substrate including a main connector and an auxiliary connector, configured to be connected to an external device; and a plurality of memory chips mounted on at least one of a first surface or a second surface of the memory substrate, wherein the main connector is disposed on one side of the memory substrate, and the auxiliary connector is disposed on the second surface of the memory substrate.

Abstract: A display device may comprise a substrate, a plurality of driving transistors on the substrate, a plurality of anode electrodes connected with the plurality of driving transistors, a light emitting layer on the plurality of anode electrodes, and a plurality of split cathode electrodes on the light emitting layer. Each of the plurality of split cathode electrodes may alternate between a first state applied with a cathode voltage and a second state of floating not applied with the cathode voltage.

Abstract: A semiconductor manufacturing apparatus may include a substrate boat configured to load a plurality of substrates; a process chamber configured to enclose the substrate boat; and a reaction tube between the substrate boat and the process chamber. The reaction tube may include a gas flowing part configured to allow for a flow of a process gas; a process part defining gas slits and an exhausting hole; and baffles on an inner side surface of the process part, excluding the exhausting hole.

Abstract: A method of updating a server knowledge graph, is performed by a server and includes obtaining a server knowledge graph of the server, and obtaining a plurality of device knowledge graphs by receiving a device knowledge graph from each of a plurality of devices. The method further includes generating a knowledge graph for server knowledge graph extension, based on the obtained plurality of device knowledge graphs, and updating the obtained server knowledge graph, using the generated knowledge graph for server knowledge graph extension.

Abstract: A method of updating a server knowledge graph, is performed by a server and includes obtaining a server knowledge graph of the server, and obtaining a plurality of device knowledge graphs by receiving a device knowledge graph from each of a plurality of devices. The method further includes generating a knowledge graph for server knowledge graph extension, based on the obtained plurality of device knowledge graphs, and updating the obtained server knowledge graph, using the generated knowledge graph for server knowledge graph extension.

Abstract: A method of updating a server knowledge graph, is performed by a server and includes obtaining a server knowledge graph of the server, and obtaining a plurality of device knowledge graphs by receiving a device knowledge graph from each of a plurality of devices. The method further includes generating a knowledge graph for server knowledge graph extension, based on the obtained plurality of device knowledge graphs, and updating the obtained server knowledge graph, using the generated knowledge graph for server knowledge graph extension.

Abstract: Methods of reducing registration errors of photomasks and photomasks formed using the methods are provided. The method may include forming a plurality of photomask patterns on a substrate and determining registration errors of the plurality of photomask patterns. The method may further include forming a plurality of stress-producing portions in the substrate to reduce the registration errors by considering exposure latitude variations.

Abstract: Methods of reducing registration errors of photomasks and photomasks formed using the methods are provided. The method may include forming a plurality of photomask patterns on a substrate and determining registration errors of the plurality of photomask patterns. The method may further include forming a plurality of stress-producing portions in the substrate to reduce the registration errors by considering exposure latitude variations.