Patents by Inventor Jeonghyun Hwang
Jeonghyun Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220173233Abstract: Structures including devices, such as transistors, integrated on a semiconductor substrate and methods of forming a structure including devices, such as transistors, integrated on a semiconductor substrate. A first transistor is formed in a first device region of a semiconductor substrate, and a second transistor is formed in a second device region of the semiconductor substrate. The second transistor includes a layer stack on the semiconductor substrate, and the layer stack includes a layer comprised of a III-V compound semiconductor material. A polycrystalline layer includes a section that is positioned in the semiconductor substrate beneath the first device region.Type: ApplicationFiled: December 2, 2020Publication date: June 2, 2022Inventors: Siva P. Adusumilli, Mark Levy, Jeonghyun Hwang
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Publication number: 20220165853Abstract: The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. More particularly, the present disclosure relates to semiconductor devices having field plates that are arranged symmetrically around a gate. The present disclosure provides a semiconductor device including an active region above a substrate, source and drain electrodes in contact with the active region, a gate above the active region and laterally between the source and drain electrodes, a first field plate between the source electrode and the gate, a second field plate between the drain electrode and the gate, in which the gate is spaced apart laterally and substantially equidistant from the first field plate and the second field plate.Type: ApplicationFiled: February 13, 2022Publication date: May 26, 2022Inventors: JOHNATAN AVRAHAM KANTAROVSKY, RAJENDRAN KRISHNASAMY, SIVA P. ADUSUMILLI, STEVEN BENTLEY, MICHAEL JOSEPH ZIERAK, JEONGHYUN HWANG
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Patent number: 11316019Abstract: The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. More particularly, the present disclosure relates to semiconductor devices having field plates that are arranged symmetrically around a gate. The present disclosure provides a semiconductor device including an active region above a substrate, source and drain electrodes in contact with the active region, a gate above the active region and laterally between the source and drain electrodes, a first field plate between the source electrode and the gate, a second field plate between the drain electrode and the gate, in which the gate is spaced apart laterally and substantially equidistant from the first field plate and the second field plate.Type: GrantFiled: July 29, 2020Date of Patent: April 26, 2022Assignee: GlobalFoundries U.S. Inc.Inventors: Johnatan Avraham Kantarovsky, Rajendran Krishnasamy, Siva P. Adusumilli, Steven Bentley, Michael Joseph Zierak, Jeonghyun Hwang
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Publication number: 20220122963Abstract: Structures including devices, such as transistors, integrated on a bulk semiconductor substrate and methods of forming a structure including devices, such as transistors, integrated on a bulk semiconductor substrate. The bulk semiconductor substrate contains a single-crystal semiconductor material having a diamond crystal lattice structure and a <111> crystal orientation. A first transistor is formed in a first device region of the bulk semiconductor substrate, and a second transistor is formed in a second device region of the bulk semiconductor substrate. The second transistor includes a layer stack on the bulk semiconductor substrate, and the layer stack includes a layer comprised of a III-V compound semiconductor material.Type: ApplicationFiled: October 16, 2020Publication date: April 21, 2022Inventors: Mark Levy, Jeonghyun Hwang, Siva P. Adusumilli
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Publication number: 20220044960Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure, including a semiconductor-based isolation structure on a substrate. A shallow trench isolation (STI) structure may be positioned on the semiconductor-based isolation structure. An active semiconductor region is on the substrate and adjacent each of the semiconductor-based isolation structure and the STI structure. The active semiconductor region includes a doped semiconductor material. At least one device on the active semiconductor region may be horizontally distal to the STI structure.Type: ApplicationFiled: October 20, 2021Publication date: February 10, 2022Inventors: Anthony K. Stamper, Henry L. Aldridge, JR., Johnatan A. Kantarovsky, Jeonghyun Hwang
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Publication number: 20220037482Abstract: The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. More particularly, the present disclosure relates to semiconductor devices having field plates that are arranged symmetrically around a gate. The present disclosure provides a semiconductor device including an active region above a substrate, source and drain electrodes in contact with the active region, a gate above the active region and laterally between the source and drain electrodes, a first field plate between the source electrode and the gate, a second field plate between the drain electrode and the gate, in which the gate is spaced apart laterally and substantially equidistant from the first field plate and the second field plate.Type: ApplicationFiled: July 29, 2020Publication date: February 3, 2022Inventors: JOHNATAN AVRAHAM KANTAROVSKY, RAJENDRAN KRISHNASAMY, SIVA P. ADUSUMILLI, STEVEN BENTLEY, MICHAEL JOSEPH ZIERAK, JEONGHYUN HWANG
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Publication number: 20210384297Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes: a first semiconductor layer including a device region; a second semiconductor layer under the first semiconductor layer; a layer of conductive material between the first semiconductor layer and the second semiconductor layer; at least one contact extending to and contacting the layer of conductive material; and a device in the device region above the layer of conductive material.Type: ApplicationFiled: June 5, 2020Publication date: December 9, 2021Inventors: Henry L. ALDRIDGE, JR., Anthony K. STAMPER, Jeonghyun HWANG, Johnatan A. KANTAROVSKY
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Patent number: 11177158Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure, including a semiconductor-based isolation structure on a substrate. A shallow trench isolation (STI) structure may be positioned on the semiconductor-based isolation structure. An active semiconductor region is on the substrate and adjacent each of the semiconductor-based isolation structure and the STI structure. The active semiconductor region includes a doped semiconductor material. At least one device on the active semiconductor region may be horizontally distal to the STI structure.Type: GrantFiled: February 25, 2020Date of Patent: November 16, 2021Assignee: GlobalFoundries U.S. Inc.Inventors: Anthony K. Stamper, Henry L. Aldridge, Jr., Johnatan A. Kantarovsky, Jeonghyun Hwang
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Patent number: 11177345Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes: a first semiconductor layer including a device region; a second semiconductor layer under the first semiconductor layer; a layer of conductive material between the first semiconductor layer and the second semiconductor layer; at least one contact extending to and contacting the layer of conductive material; and a device in the device region above the layer of conductive material.Type: GrantFiled: June 5, 2020Date of Patent: November 16, 2021Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Henry L. Aldridge, Jr., Anthony K. Stamper, Jeonghyun Hwang, Johnatan A. Kantarovsky
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Publication number: 20210265198Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure, including a semiconductor-based isolation structure on a substrate. A shallow trench isolation (STI) structure may be positioned on the semiconductor-based isolation structure. An active semiconductor region is on the substrate and adjacent each of the semiconductor-based isolation structure and the STI structure. The active semiconductor region includes a doped semiconductor material. At least one device on the active semiconductor region may be horizontally distal to the STI structure.Type: ApplicationFiled: February 25, 2020Publication date: August 26, 2021Inventors: Anthony K. Stamper, Henry L. Aldridge, JR., Johnatan A. Kantarovsky, Jeonghyun Hwang
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Patent number: 7993938Abstract: A method of forming a highly doped layer of AlGaN, is practiced by first removing contaminants from a MBE machine. Wafers are then outgassed in the machine at very low pressures. A nitride is then formed on the wafer and an AlN layer is grown. The highly doped GaAlN layer is then formed having electron densities beyond 1×1020 cm?3 at Al mole fractions up to 65% are obtained. These levels of doping application of n-type bulk, and n/p tunnel injection to short wavelength UV emitters. Some applications include light emitting diodes having wavelengths between approximately 254 and 290 nm for use in fluorescent light bulbs, hazardous materials detection, water purification and other decontamination environments. Lasers formed using the highly doped layers are useful in high-density storage applications or telecommunications applications. In yet a further embodiment, a transistor is formed utilizing the highly doped layer as a channel.Type: GrantFiled: January 27, 2009Date of Patent: August 9, 2011Assignee: Cornell Research Foundation, Inc.Inventors: William J. Schaff, Jeonghyun Hwang
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Patent number: 7622322Abstract: A passivation layer of AlN is deposited on a GaN channel HFET using molecular beam epitaxy (MBE). Using MBE, many other surfaces may also be coated with AlN, including silicon devices, nitride devices, GaN based LEDs and lasers as well as other semiconductor systems. The deposition is performed at approximately 150° C. and uses alternating beams of aluminum and remote plasma RF nitrogen to produce an approximately 500 ? thick AlN layer.Type: GrantFiled: May 15, 2001Date of Patent: November 24, 2009Assignee: Cornell Research Foundation, Inc.Inventors: William J. Schaff, Jeonghyun Hwang, Bruce M. Green
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Publication number: 20090165816Abstract: A method of forming a highly doped layer of AlGaN, is practiced by first removing contaminants from a MBE machine. Wafers are then outgassed in the machine at very low pressures. A nitride is then formed on the wafer and an AlN layer is grown. The highly doped GaAlN layer is then formed having electron densities beyond 1×1020 cm?3 at Al mole fractions up to 65% are obtained. These levels of doping application of n-type bulk, and n/p tunnel injection to short wavelength UV emitters. Some applications include light emitting diodes having wavelengths between approximately 254 and 290 nm for use in fluorescent light bulbs, hazardous materials detection, water purification and other decontamination environments. Lasers formed using the highly doped layers are useful in high-density storage applications or telecommunications applications. In yet a further embodiment, a transistor is formed utilizing the highly doped layer as a channel.Type: ApplicationFiled: January 27, 2009Publication date: July 2, 2009Applicant: Cornell Research Foundation, Inc.Inventors: William J. Schaff, Jeonghyun Hwang
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Patent number: 7485901Abstract: A wide bandgap semiconductor material is heavily doped to a degenerate level. Impurity densities approaching 1% of the volume of the semiconductor crystal are obtained to greatly increase conductivity. In one embodiment, a layer of AlGaN is formed on a wafer by first removing contaminants from a MBE machine. Wafers are then outgassed in the machine at very low pressures. A nitride is then formed on the wafer and an AlN layer is grown. The highly doped GaAlN layer is then formed having electron densities beyond 1×1020 cm?3 at Al mole fractions up to 65% are obtained.Type: GrantFiled: March 16, 2005Date of Patent: February 3, 2009Assignee: Cornell Research Foundation Inc.Inventors: William J. Schaff, Jeonghyun Hwang
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Patent number: 7482191Abstract: A method of forming a highly doped layer of AlGaN, is practiced by first removing contaminants from a MBE machine. Wafers are then outgassed in the machine at very low pressures. A nitride is then formed on the wafer and an AlN layer is grown. The highly doped GaAlN layer is then formed having electron densities beyond 1×1020 cm?3 at Al mole fractions up to 65% are obtained. These levels of doping application of n-type bulk, and n/p tunnel injection to short wavelength UV emitters. Some applications include light emitting diodes having wavelengths between approximately 254 and 290 nm for use in fluorescent light bulbs, hazardous materials detection, water purification and other decontamination environments. Lasers formed using the highly doped layers are useful in high-density storage applications or telecommunications applications. In yet a further embodiment, a transistor is formed utilizing the highly doped layer as a channel.Type: GrantFiled: March 17, 2005Date of Patent: January 27, 2009Assignee: Cornell Research Foundation, Inc.Inventors: William J. Schaff, Jeonghyun Hwang
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Patent number: 6953740Abstract: A wide bandgap semiconductor material is heavily doped to a degenerate level. Impurity densities approaching 1% of the volume of the semiconductor crystal are obtained to greatly increase conductivity. In one embodiment, a layer of AlGaN is formed on a wafer by first removing contaminants from a MBE machine. Wafers are then outgassed in the machine at very low pressures. A nitride is then formed on the wafer and an AlN layer is grown. The highly doped GaAlN layer is then formed having electron densities beyond 1×1020 cm?3 at Al mole fractions up to 65% are obtained.Type: GrantFiled: May 15, 2002Date of Patent: October 11, 2005Assignee: Cornell Research Foundation, Inc.Inventors: William J. Schaff, Jeonghyun Hwang
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Publication number: 20050179047Abstract: A method of forming a highly doped layer of AlGaN, is practiced by first removing contaminants from a MBE machine. Wafers are then outgassed in the machine at very low pressures. A nitride is then formed on the wafer and an AlN layer is grown. The highly doped GaAlN layer is then formed having electron densities beyond 1×1020 cm?3 at Al mole fractions up to 65% are obtained. These levels of doping application of n-type bulk, and n/p tunnel injection to short wavelength UV emitters. Some applications include light emitting diodes having wavelengths between approximately 254 and 290 nm for use in fluorescent light bulbs, hazardous materials detection, water purification and other decontamination environments. Lasers formed using the highly doped layers are useful in high-density storage applications or telecommunications applications. In yet a further embodiment, a transistor is formed utilizing the highly doped layer as a channel.Type: ApplicationFiled: March 17, 2005Publication date: August 18, 2005Inventors: William Schaff, Jeonghyun Hwang
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Publication number: 20050179050Abstract: A wide bandgap semiconductor material is heavily doped to a degenerate level. Impurity densities approaching 1% of the volume of the semiconductor crystal are obtained to greatly increase conductivity. In one embodiment, a layer of AlGaN is formed on a wafer by first removing contaminants from a MBE machine. Wafers are then outgassed in the machine at very low pressures. A nitride is then formed on the wafer and an AIN layer is grown. The highly doped GaAlN layer is then formed having electron densities beyond 1×1020 cm?3 at Al mole fractions up to 65% are obtained.Type: ApplicationFiled: March 16, 2005Publication date: August 18, 2005Inventors: William Schaff, Jeonghyun Hwang
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Patent number: 6888170Abstract: A method of forming a highly doped layer of AlGaN, is practiced by first removing contaminants from a MBE machine. Wafers are then outgassed in the machine at very low pressures. A nitride is then formed on the wafer and an AlN layer is grown. The highly doped GaAlN layer is then formed having electron densities beyond 1×1020 cm?3 at Al mole fractions up to 65% are obtained. These levels of doping application of n-type bulk, and n/p tunnel injection to short wavelength UV emitters. Some applications include light emitting diodes having wavelengths between approximately 254 and 290 nm for use in fluorescent light bulbs, hazardous materials detection, water purification and other decontamination environments. Lasers formed using the highly doped layers are useful in high-density storage applications or telecommunications applications. In yet a further embodiment, a transistor is formed utilizing the highly doped layer as a channel.Type: GrantFiled: May 7, 2002Date of Patent: May 3, 2005Assignee: Cornell Research Foundation, Inc.Inventors: William J. Schaff, Jeonghyun Hwang
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Publication number: 20030176003Abstract: A wide bandgap semiconductor material is heavily doped to a degenerate level. Impurity densities approaching 1% of the volume of the semiconductor crystal are obtained to greatly increase conductivity. In one embodiment, a layer of AlGaN is formed on a wafer by first removing contaminants from a MBE machine. Wafers are then outgassed in the machine at very low pressures. A nitride is then formed on the wafer and an AlN layer is grown. The highly doped GaAlN layer is then formed having electron densities beyond 1×1020 cm−3 at Al mole fractions up to 65% are obtained.Type: ApplicationFiled: May 15, 2002Publication date: September 18, 2003Inventors: William J. Schaff, Jeonghyun Hwang