Patents by Inventor Jeong Ki Choi

Jeong Ki Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240164081
    Abstract: A semiconductor device includes a substrate including a logic cell region and a connection region, a dummy transistor on the connection region, an intermediate connection layer on the dummy transistor, the intermediate connection layer including a connection pattern electrically connected to the dummy transistor, a first metal layer on the intermediate connection layer, an etch stop layer between the intermediate connection layer and the first metal layer, the etch stop layer covering a top surface of the connection pattern, and a penetration contact extended from the first metal layer toward a bottom surface of the substrate penetrating the connection region.
    Type: Application
    Filed: January 5, 2024
    Publication date: May 16, 2024
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Shaofeng DING, Jeong Hoon AHN, Yun Ki CHOI
  • Patent number: 11983501
    Abstract: The present invention relates to an apparatus and method for automatically generating machine reading comprehension training data, and more particularly, to an apparatus and method for automatically generating and managing machine reading comprehension training data based on text semantic analysis. The apparatus for automatically generating machine reading comprehension training data according to the present invention includes a domain selection text collection unit configured to collect pieces of text data according to domains and subjects, a paragraph selection unit configured to select a paragraph using the pieces of collected text data and determine whether questions and correct answers are generatable, and a question and correct answer generation unit configured to generate questions and correct answers from the selected paragraph.
    Type: Grant
    Filed: October 7, 2021
    Date of Patent: May 14, 2024
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Yong Jin Bae, Joon Ho Lim, Min Ho Kim, Hyun Kim, Hyun Ki Kim, Ji Hee Ryu, Kyung Man Bae, Hyung Jik Lee, Soo Jong Lim, Myung Gil Jang, Mi Ran Choi, Jeong Heo
  • Publication number: 20240154042
    Abstract: A semiconductor device includes a substrate including an upper surface and a lower surface that are opposite to each other in a first direction, an active pattern which is on the upper surface of the substrate and extends in a second direction, a gate electrode which is on the active pattern and extends in a third direction, a first source/drain pattern which is connected to the active pattern on the upper surface of the substrate, and includes a lower epitaxial region and an upper epitaxial region, the upper epitaxial region including an epitaxial recess, and the lower epitaxial region being inside the epitaxial recess, a first source/drain contact, which is connected to the first source/drain pattern and extends into the substrate, and a contact silicide layer, which is between the first source/drain contact and the first source/drain pattern and contacts the lower epitaxial region.
    Type: Application
    Filed: July 17, 2023
    Publication date: May 9, 2024
    Inventors: Jun Ki PARK, Wan Don KIM, Jeong Hyuk YIM, Hyo Seok CHOI, Sung Hwan KIM
  • Patent number: 11961882
    Abstract: A semiconductor device includes a semiconductor substrate including a connection region, a pair of epitaxial patterns provided at the semiconductor substrate, a capacitor disposed between the pair of epitaxial patterns, a middle connection layer on the capacitor, an interconnection layer on the middle connection layer, and a through-via provided under the interconnection layer and penetrating the connection region of the semiconductor substrate. The capacitor includes an upper portion of the semiconductor substrate between the pair of epitaxial patterns, a metal electrode on the upper portion of the semiconductor substrate, and a dielectric pattern disposed between the upper portion of the semiconductor substrate and the metal electrode. The through-via is connected to the capacitor through the interconnection layer and the middle connection layer.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: April 16, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Shaofeng Ding, Jeong Hoon Ahn, Yun Ki Choi
  • Publication number: 20240105556
    Abstract: A semiconductor device includes a substrate provided with an integrated circuit and a contact, an interlayer dielectric layer covering the integrated circuit and the contact, a through electrode penetrating the substrate and the interlayer dielectric layer, a first intermetal dielectric layer on the interlayer dielectric layer, and first and second wiring patterns in the first intermetal dielectric layer. The first wiring pattern includes a first conductive pattern on the through electrode, and a first via penetrating the first intermetal dielectric layer and connecting the first conductive pattern to the through electrode. The second wiring pattern includes a second conductive pattern on the contact, and a second via penetrating the first intermetal dielectric layer and connecting the second conductive pattern to the contact. A first width in a first direction of the first via is greater than a second width in the first direction of the second via.
    Type: Application
    Filed: December 5, 2023
    Publication date: March 28, 2024
    Inventors: SHAOFENG DING, JEONG HOON AHN, YUN KI CHOI
  • Publication number: 20100073081
    Abstract: An integrated tracking filter includes: an amplifying unit having first to third terminals, the first terminal being connected to an input stage and the second terminal being connected to an output stage, and amplifying a signal from the input stage; a loading unit connected between a power source stage and the second terminal of the amplifying unit; a current source connected between the third terminal of the amplifying unit and a ground; and a switched LC filter unit connected between the third terminal of the amplifying unit and the ground and varying a pass band of the signal.
    Type: Application
    Filed: February 27, 2009
    Publication date: March 25, 2010
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Yo Sub MOON, Jeong Ki Choi, Yoo Hwan Kim, Gyu Suck Kim, Kyoung Seok Park
  • Patent number: 7627295
    Abstract: A downconverter and upconverter are provided which can obtain a sufficient image rejection ratio in a low-Intermediate Frequency (IF) scheme while reducing power consumption and can suppress Error Vector Magnitude (EVM)-related degradation in a zero-IF scheme. A complex-coefficient transversal filter rejects one side of a positive or negative frequency, and converts a Radio Frequency (RF) signal to a complex RF signal configured by real and imaginary parts. A local oscillator outputs a real local signal with a set frequency. A half-complex mixer, connected to the complex-coefficient transversal filter and the local oscillator, performs a frequency conversion process by multiplying the complex RF signal output from the complex-coefficient transversal filter and the real local signal output from the local oscillator, and outputs a complex signal of a frequency separated by the set frequency from a frequency of the RF signal.
    Type: Grant
    Filed: April 13, 2006
    Date of Patent: December 1, 2009
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Kishi Takahiko, Sato Takahiro, Won-Jin Baek, Jeong-Ki Choi
  • Publication number: 20090280762
    Abstract: A mixer includes, an input current generation unit generating an input current; a first path circuit unit including n number of transistors having sources connected in common to an output node of the input current generation unit; and a second path circuit unit including n number of transistors having sources connected in common to the output node of the input current generation unit, and respectively corresponding to the n number of transistors included in the first path circuit unit. Local oscillator signals sequentially phase-shifted by 180°/n are individually input to gates of the n number of transistors included in the first path circuit unit, and local oscillator signals having opposite phases to the local oscillator signals input to the gates of the corresponding transistors included in the first path circuit unit are individually input to gates of the n number of transistors included in the second path circuit unit.
    Type: Application
    Filed: October 28, 2008
    Publication date: November 12, 2009
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Kyoung Seok PARK, Nam Heung KIM, Jeong Ki CHOI, Yo Sub MOON, Gyu Suck KIM, Seung Won SEO, Yoo Hwan KIM
  • Patent number: 7514980
    Abstract: The present invention relates to an exponential function generator which is realized with only CMOS element without BJT element, not limited by the physical properties of the element or a square circuit, and not complicated in its configuration, and a variable gain amplifier using the same. The exponential function generator includes a voltage-current converter, 1st to nth curve generators for mirroring the current from the voltage-current converter, outputting a current adjusted according to a predetermined ratio, and an output end for outputting the sum of the current from the 1st to nth curve generators. The exponential current generator is configured to generate the current exponentially adjusted according to the control voltage.
    Type: Grant
    Filed: May 26, 2006
    Date of Patent: April 7, 2009
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jeong Ki Choi, Won Jin Baek, Hyun Hwan Yoo, Seung Min Oh
  • Publication number: 20060293012
    Abstract: The present invention relates to a terrestrial DMB receiver capable of eliminating image noise and minimizing the number of external elements. In the invention, a terrestrial DMB signal is down-converted into a baseband I/Q signal and then up-converted into a predetermined intermediate frequency signal. The invention solves the problematic image noise and minimizes the number of external elements at the same time.
    Type: Application
    Filed: June 2, 2006
    Publication date: December 28, 2006
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: BYEONG HAK JO, WON JIN BAEK, JEONG KI CHOI, KYUNG SEOK PARK
  • Publication number: 20060256216
    Abstract: A downconverter and upconverter are provided which can obtain a sufficient image rejection ratio in a low-Intermediate Frequency (IF) scheme while reducing power consumption and can suppress Error Vector Magnitude (EVM)-related degradation in a zero-IF scheme. A complex-coefficient transversal filter rejects one side of a positive or negative frequency, and converts a Radio Frequency (RF) signal to a complex RF signal configured by real and imaginary parts. A local oscillator outputs a real local signal with a set frequency. A half-complex mixer, connected to the complex-coefficient transversal filter and the local oscillator, performs a frequency conversion process by multiplying the complex RF signal output from the complex-coefficient transversal filter and the real local signal output from the local oscillator, and outputs a complex signal of a frequency separated by the set frequency from a frequency of the RF signal.
    Type: Application
    Filed: April 13, 2006
    Publication date: November 16, 2006
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kishi Takahiko, Sato Takahiro, Won-Jin Baek, Jeong-Ki Choi
  • Patent number: 7076221
    Abstract: Disclosed herein is a digital automatic fine tuning method and apparatus, which is capable of detecting a difference between a nominal frequency and an intermediate frequency generated in a tuner using a counter, and applying the counted data of the counter as a fine tuning value for the intermediate frequency without using a decoder by controlling the reset and preset operations of the counter that counts the frequency of the intermediate frequency.
    Type: Grant
    Filed: October 30, 2003
    Date of Patent: July 11, 2006
    Assignee: Samsung Electro-Mechanics Co., Ltd
    Inventors: Young Jin Lee, Hyo Seok Kwon, Won Jin Baek, Jin Taek Lee, Hyun Hwan Yoo, Jeong Ki Choi
  • Publication number: 20050048936
    Abstract: Disclosed herein is a digital automatic fine tuning method and apparatus, which is capable of detecting a difference between a nominal frequency and an intermediate frequency generated in a tuner using a counter, and applying the counted data of the counter as a fine tuning value for the intermediate frequency without using a decoder by controlling the reset and preset operations of the counter that counts the frequency of the intermediate frequency.
    Type: Application
    Filed: October 30, 2003
    Publication date: March 3, 2005
    Inventors: Young Jin Lee, Hyo Seok Kwon, Won Jin Baek, Jin Taek Lee, Hyun Hwan Yoo, Jeong Ki Choi