Abstract: An apparatus and method for measuring air currents on the surface of a substrate, which can accurately measure the magnitude and direction of air currents on the surface of a wafer with wafer-type air current measurement sensors, are provided. The apparatus includes: a first air current measurement module measuring a magnitude of air currents on a surface of a first substrate, which is processed in accordance with a semiconductor manufacturing process; a second air current measurement module measuring a movement direction of the air currents; and a power module supplying power to the first and second air current measurement modules, wherein the first air current measurement module, the second air current measurement module, and the power module are mounted on a second substrate, which has the same shape as the first substrate.

Abstract: The inventive concepts provide a temperature controller for performing a comparative measurement process and a sensing calibration process without separating a temperature sensor and an input channel, if a comparative measurement process and a sensing calibration process of a temperature sensor for controlling a temperature of a semiconductor manufacturing facility are performed.

Abstract: A semiconductor chip includes a base of a memory transistor in a first region of a substrate, and a base of a metal oxide semiconductor (MOS) transistor in a second region of the substrate. The base of the memory transistor includes a channel in a surface of substrate, a tunnel layer over the channel, and a nitride layer over the tunnel layer. The base of the MOS transistor includes a channel in the surface of substrate. The MOS transistor is coupled to the memory transistor through a shared diffusion region formed in the surface of substrate between the channel of the MOS transistor and the channel of the memory transistor. A plasma oxide overlying the nitride layer and the surface of the substrate to form a top oxide layer over the nitride layer and a gate oxide layer over the surface of substrate in the second region.

Abstract: Systems and methods of the present invention may be used to charge a layer (such as a passivation layer and/or antireflective layer) of a solar cell (e.g., wafer) with a positive or negative charge. The layer may retain the charge to improve operation of the solar cell. The charged layer may include any suitable dielectric material capable of retaining either a negative or a positive charge. Systems and methods of the present invention permit in-situ charging of a layer. Charging of a layer may be accomplished during or after deposition of the layer including after completing the whole solar cell process, in other words, on a finished cell.

Abstract: Embodiments of the present invention help prevent Potential-Induced Degradation (PID) in solar cell modules. A solar cell module according to one embodiment of the present invention comprises a glass sheet, a frame covering at least a portion of the glass sheet, a plurality of solar cells at least partially covered by the glass sheet, and a hydrophobic coating covering at least a portion of the frame and at least a portion of the glass sheet.

Abstract: Systems and methods of the present invention may be used to charge a layer (such as a passivation layer and/or antireflective layer) of a solar cell (e.g., wafer) with a positive or negative charge. The layer may retain the charge to improve operation of the solar cell. The charged layer may include any suitable dielectric material capable of retaining either a negative or a positive charge. Systems and methods of the present invention permit in-situ charging of a layer. Charging of a layer may be accomplished during or after deposition of the layer including after completing the whole solar cell process, in other words, on a finished cell.

Abstract: Systems and methods of the present invention may be used to charge a layer (such as a passivation layer and/or antireflective layer) of a solar cell (e.g., wafer) with a positive or negative charge. The layer may retain the charge to improve operation of the solar cell. The charged layer may include any suitable dielectric material capable of retaining either a negative or a positive charge. Systems and methods of the present invention permit in-situ charging of a layer. Charging of a layer may be accomplished during or after deposition of the layer including after completing the whole solar cell process, in other words, on a finished cell.

Abstract: Systems and methods of the present invention may be used to charge a layer (such as a passivation layer and/or antireflective layer) of a solar cell (e.g., wafer) with a positive or negative charge. The layer may retain the charge to improve operation of the solar cell. The charged layer may include any suitable dielectric material capable of retaining either a negative or a positive charge. Systems and methods of the present invention permit in-situ charging of a layer. Charging of a layer may be accomplished during or after deposition of the layer including after completing the whole solar cell process, in other words, on a finished cell.

Abstract: Systems and methods of the present invention can be used to charge a charge-holding layer (such as a passivation layer and/or antireflective layer) of a solar cell with a positive or negative charge as desired. The charge-holding layer(s) of such a cell can include any suitable dielectric material capable of holding either a negative or a positive charge, and can be charged at any suitable point during manufacture of the cell, including during or after deposition of the passivation layer(s). A method according to one aspect of the invention includes disposing a solar cell in electrical communication with an electrode inside a chamber. The solar cell includes an emitter, a base, a first passivation layer adjacent the emitter, and a second passivation layer adjacent the base. Gas is injected into the chamber and a plasma (with photons having an energy level of at least about 3.1 eV) is generated using the gas.

Abstract: A method for semiconductor fabrication. The method includes providing a silicon substrate and forming a tunnel oxide layer over the silicon substrate. Thereafter, a nitride layer is formed over the tunnel oxide layer. The nitride layer and the tunnel oxide layer are etched except where at least one nonvolatile silicon oxide nitride oxide silicon (SONOS) transistor is formed. Additionally, oxide layers are simultaneously formed over the nitride layer corresponding to where at bast one SONOS memory transistor is formed and over the exposed silicon substrate corresponding to where at least one metal oxide semiconductor (MOS) transistor is formed.

Abstract: The present invention relates to the charge control of the front and back passivation layers of a solar cell, which allows a common passivation material to be used on both the front and back surfaces of a solar cell. A solar cell according to one embodiment of the present invention comprises an emitter and a base. The cell further includes a first passivation layer adjacent the emitter, the first passivation layer having a charge. The cell also includes a second passivation layer adjacent the base, the second passivation layer having a charge opposite to the charge of the first passivation layer, wherein the first passivation layer and the second passivation layer include a common passivation material.

Abstract: A method of operating a nonvolatile memory circuit having a plurality of transistors arranged in series between a voltage/current source node and recall sink node includes asserting a gate bias on an isolation transistor between the source node and a charge storage transistor during nonvolatile STANDBY.

Abstract: A method of operating a nonvolatile memory circuit having a plurality of transistors arranged in series between a voltage/current source node and recall sink node includes asserting a gate bias on an isolation transistor between the source node and a charge storage transistor during nonvolatile STANDBY.

Abstract: A method for semiconductor fabrication. The method includes providing a silicon substrate and forming a tunnel oxide layer the silicon substrate. Thereafter, a nitride layer is formed over the tunnel oxide layer. The nitride layer and the tunnel oxide layer are etched except where at least one nonvolatile silicon oxide nitride oxide silicon (SONOS) transistor is formed. Additionally, oxide layers are simultaneously formed over the nitride layer corresponding to where at least one SONOS memory transistor is formed and over the exposed silicon substrate corresponding to where at least one metal oxide semiconductor (MOS) transistor is formed.

Abstract: A method for forming a dual gate of a semiconductor device includes the steps of sequentially stacking a gate insulating film, a semiconductor layer, and a low resistance metal layer on a semiconductor substrate having a first well of a first conductivity type and a second well of a second conductivity type, forming first and second gate patterns that include the semiconductor layer and the low resistance metal layer on the substrate corresponding to the first and second wells, forming sidewall spacers at sides of the first and second gate patterns, and exposing the first well and the first gate pattern, implanting impurity ions of the second conductivity type into the exposed first well and the first gate pattern to form a first source and a first drain, exposing the second well and the second gate pattern, implanting impurity ions of the first conductivity type into the exposed second well and the second gate pattern to form a second source and a second drain; and diffusing the impurity ions from the low re

Abstract: A semiconductor device and a method for fabricating the same are disclosed, in which floating body effect is reduced by applying a bias to a body in an SOI MOSFET. The semiconductor device includes first and second impurity ion implanting layers of a conductivity type formed in a semiconductor substrate having a buried oxide film and surface silicon layers thereon, first and second transistors of a conductivity type respectively formed on the first and second impurity ion implanting layers, having source/drain regions and a gate, trenches formed between the first and second transistors, single crystal silicon layers connected to any one of the source/drain regions of the respective transistors and the first and second impurity ion implanting layers at sides of the trenches, and carrier exhausting electrodes connected to the first and second impurity ion implanting layers at one sides of the respective transistors, for exhausting carrier generated by ionization impact in the respective transistors.

Abstract: Methods of forming a MOS transistor having dual gates minimizes impurity channeling and diffusion that can occur during impurity injection and activating processes. A method of fabricating the transistor includes the steps of forming a first conduction type well and a second conduction type well in a semiconductor substrate having an isolation region and an active region formed therein. Then, a gate oxide film is formed on an entire surface of the substrate, and a polysilicon layer is deposited on the gate oxide film preferably at a temperature of about 660° C. to about 700° C. and a pressure of about 10 to about 300 Torr. Next, portions of the polysilicon layer and the gate oxide film are selectively removed to form a gate electrode on each of the wells. Impurity ions are injected, having a conduction type opposite a conduction type of the corresponding well, into an exposed surface of each of the wells, to form lightly doped impurity regions.

Abstract: A semiconductor device and a method for fabricating the same are disclosed, in which floating body effect is reduced by applying a bias to a body in an SOI MOSFET. The semiconductor device includes first and second impurity ion implanting layers of a conductivity type formed in a semiconductor substrate having a buried oxide film and surface silicon layers thereon, first and second transistors of a conductivity type respectively formed on the first and second impurity ion implanting layers, having source/drain regions and a gate, trenches formed between the first and second transistors, single crystal silicon layers connected to any one of the source/drain regions of the respective transistors and the first and second impurity ion implanting layers at sides of the trenches, and carrier exhausting electrodes connected to the first and second impurity ion implanting layers at one sides of the respective transistors, for exhausting carrier generated by ionization impact in the respective transistors.

Abstract: A semiconductor device and a method for fabricating the same are disclosed, in which floating body effect is reduced by applying a bias to a body in an SOI MOSFET. The semiconductor device includes first and second impurity ion implanting layers of a conductivity type formed in a semiconductor substrate having a buried oxide film and surface silicon layers thereon, first and second transistors of a conductivity type respectively formed on the first and second impurity ion implanting layers, having source/drain regions and a gate, trenches formed between the first and second transistors, single crystal silicon layers connected to any one of the source/drain regions of the respective transistors and the first and second impurity ion implanting layers at sides of the trenches, and carrier exhausting electrodes connected to the first and second impurity ion implanting layers at one sides of the respective transistors, for exhausting carrier generated by ionization impact in the respective transistors.

Abstract: A method for manufacturing a semiconductor device improves hot carrier characteristic in a device having a thick gate insulating film without being affected by short channel effect, thereby improving reliability of the device. The method for manufacturing a semiconductor device includes the steps of forming gate electrodes having gate insulating films of different thicknesses on a semiconductor substrate, implanting a low-concentration impurity ion into the semiconductor substrate at both sides of the gate electrodes, implanting a nitrogen ion into a portion, where the low-concentration impurity ion is implanted, in the gate insulating film relatively thicker than the other gate insulating film, forming sidewall spacers at both sides of the gate electrodes, and implanting a high-concentration source/drain impurity ion into the semiconductor substrate.