Patents by Inventor Jeong Oen Lee

Jeong Oen Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190133442
    Abstract: By adopting nature's biopolymer-phase-separation process, a highly scalable biomimetic bottom-up nanofabrication method is developed to create low-aspect-ratio bioinspired nanostructures (BINS) on freestanding silicon-nitride (Si3N4) membranes. Unlike previous high-aspect-ratio nonstructures that focused on replicating optical antireflection and bactericidal properties, the IOP sensor with BINS (or BINS-IOP sensor) of the present disclosure has a pseudo-periodic arrangement and dimensions that control short-range scattering to enhance omnidirectional optical transmission and angle independence while also exhibiting anti-biofouling properties of high-aspect-ratio nanostructures, which typically rely on physical cell lysis. In some embodiments, the BINS-IOP sensor can have a low-aspect-ratio, which displays strong hydrophilicity to form an aqueous anti-adhesion barrier for proteins and cellular fouling without cell lysis.
    Type: Application
    Filed: September 5, 2018
    Publication date: May 9, 2019
    Inventors: Vinayak Narasimhan, Radwanul H. Siddique, Jeong Oen Lee, Hyuck Choo
  • Patent number: 8956962
    Abstract: A method for fabricating a large-area nanoscale pattern includes: forming multilayer main thin films isolated by passivation layers; patterning a first main thin film to form a first main pattern; forming a first spacer pattern with respect to the first main pattern; and forming a second main pattern by transferring the first spacer pattern onto a second main thin film. By using multilayer main thin films isolated by different passivation films, spacer lithography capable of reducing a pattern pitch can be repetitively performed, and the pattern pitch is repetitively reduced without shape distortion after formation of micrometer-scale patterns, thereby forming nanometer-scale fine patterns uniformly over a wide area.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: February 17, 2015
    Assignee: LG Innotek Co., Ltd.
    Inventors: Young-Jae Lee, Kyoung Jong Yoo, Jin Su Kim, Jun Lee, Yong In Lee, JunBo Yoon, JeongHo Yeon, Joo-Hyung Lee, Jeong Oen Lee
  • Publication number: 20120156882
    Abstract: A method for fabricating a large-area nanoscale pattern includes: forming multilayer main thin films isolated by passivation layers; patterning a first main thin film to form a first main pattern; forming a first spacer pattern with respect to the first main pattern; and forming a second main pattern by transferring the first spacer pattern onto a second main thin film. By using multilayer main thin films isolated by different passivation films, spacer lithography capable of reducing a pattern pitch can be repetitively performed, and the pattern pitch is repetitively reduced without shape distortion after formation of micrometer-scale patterns, thereby forming nanometer-scale fine patterns uniformly over a wide area.
    Type: Application
    Filed: September 23, 2011
    Publication date: June 21, 2012
    Applicant: LG Innotek Co., Ltd.
    Inventors: YOUNG-JAE LEE, KYOUNG JONG YOO, JIN SU KIM, JUN LEE, YONG IN LEE, JUNBO YOON, JEONGHO YEON, JOO-HYUNG LEE, JEONG OEN LEE
  • Patent number: 7787276
    Abstract: A method for controlling a memory array using a mechanical switch according to the present invention, in which the memory array comprises; a plurality of word lines; a plurality of bit lines intersecting each other with the plurality of word lines; a gate electrode connected to each of the word lines; a drain electrode spaced apart from the gate electrode and connected to a capacitor; and a source electrode comprises: an anchor part spaced apart from the gate electrode and connected to each of the bit lines; a mobile part where a dimple is formed, comprises the steps of: applying a first voltage V1 to the bit line selected from the plurality of bit lines; applying a second voltage V2 greater than a sum of the first voltage V1 and a pull-in voltage Vpi to the word lines selected from the plurality of word lines; and applying a voltage smaller than a sum of a erase voltage Verase and the pull-in voltage Vpi and a voltage greater than a difference between a write voltage Vwrite and the pull-in voltage Vpi to the
    Type: Grant
    Filed: May 16, 2008
    Date of Patent: August 31, 2010
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Jun-Bo Yoon, Weon-Wi Jang, Jeong-Oen Lee
  • Patent number: 7744947
    Abstract: A method of fabricating a semiconductor device by filling carbon nanotubes in a recess is disclosed. The method of fabricating the semiconductor device comprises patterning a mold on a substrate, coating carbon nanotubes on an entire surface of the recess and the mold formed by the patterning, filling the carbon nanotubes coated on the an entire surface of the mold in the recess, and removing the mold.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: June 29, 2010
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Byung Chul Lee, Jeong Oen Lee, Yang Kyu Choi, Jun-Bo Yoon
  • Publication number: 20100130005
    Abstract: A method of fabricating a semiconductor device by filling carbon nanotubes in a recess is disclosed. The method of fabricating the semiconductor device comprises patterning a mold on a substrate, coating carbon nanotubes on an entire surface of the recess and the mold formed by the patterning, filling the carbon nanotubes coated on the an entire surface of the mold in the recess, and removing the mold.
    Type: Application
    Filed: July 31, 2006
    Publication date: May 27, 2010
    Inventors: Byung Chul Lee, Jeong Oen Lee, Yang Kyu Choi, Jun-Bo Yoon
  • Patent number: 7486539
    Abstract: Provided are a memory array using a mechanical switch, a method for controlling the same, a display apparatus using a mechanical switch, and a method for controlling the same. The memory array comprises a plurality of word lines, a plurality of bit lines intersecting each other with the plurality of word lines, and a plurality of the mechanical switches. The mechanical switch comprises a gate electrode, a drain electrode, and a source electrode.
    Type: Grant
    Filed: November 3, 2006
    Date of Patent: February 3, 2009
    Assignee: Korea Advanced Instutute of Science & Technology
    Inventors: Weon Wi Jang, O-Deuk Kwon, Jeong Oen Lee, Jun-Bo Yoon
  • Publication number: 20090021972
    Abstract: A method for controlling a memory array using a mechanical switch according to the present invention, in which the memory array comprises; a plurality of word lines; a plurality of bit lines intersecting each other with the plurality of word lines; a gate electrode connected to each of the word lines; a drain electrode spaced apart from the gate electrode and connected to a capacitor; and a source electrode comprises: an anchor part spaced apart from the gate electrode and connected to each of the bit lines; a mobile part where a dimple is formed, comprises the steps of: applying a first voltage V1 to the bit line selected from the plurality of bit lines; applying a second voltage V2 greater than a sum of the first voltage V1 and a pull-in voltage Vpi to the word lines selected from the plurality of word lines; and applying a voltage smaller than a sum of a erase voltage Verase and the pull-in voltage Vpi and a voltage greater than a difference between a write voltage Vwrite and the pull-in voltage Vpi to the
    Type: Application
    Filed: May 16, 2008
    Publication date: January 22, 2009
    Inventors: Jun-Bo Yoon, Jeong-Oen Lee, Weon-Wi Jang