Abstract: A semiconductor package includes: a redistribution substrate including a connection via and a redistribution layer electrically connected to each other, and a redistribution pad electrically connected to the redistribution layer by the connection via, a space pattern separating at least some of the redistribution pads from each other, a dummy metal pattern at least partially surrounded by the space pattern, and a degassing opening passing through at least one of the redistribution pad and the dummy metal pattern; a connection bump electrically connected to the redistribution pad; and a semiconductor chip on the redistribution substrate and including a connection pad electrically connected to the redistribution layer, the redistribution pad including a plurality of protrusions protruding from the same plane in directions different from each other and having a corner having a rounded shape, and the dummy metal pattern includes branch patterns each extending in directions different from one another.

Abstract: A gate driver circuit can include a plurality of stage circuits, in which each of the plurality of stage circuits supplies a gate signal to gate lines arranged in a display panel, and includes an M node, a Q node, a QH node, a QB node, a line selector, a Q node controller, a Q node and QH node stabilizer, an inverter, a QB node stabilizer, a carry signal output circuit portion, a gate signal output circuit portion, and a Q node bootstrapper, in which the Q node bootstrapper is connected between the carry signal output circuit portion and the gate signal output circuit portion, or the gate signal output circuit portion is connected between the carry signal output circuit portion and the Q node bootstrapper.

Abstract: A semiconductor package includes a redistribution layer, a semiconductor chip disposed on the redistribution layer and an expanded layer surrounding the semiconductor chip, connection terminals on the expanded layer, and a wiring structure electrically connecting the redistribution layer to the connection terminals. Each of the connection terminal includes a seed layer, a terminal base layer including a terminal groove exposing a part of an upper surface of the seed layer on the seed layer and formed of a first metal, a terminal cover layer including a barrier portion filling the terminal groove and a cover base portion covering the barrier portion and the terminal base layer and formed of a second metal, and a terminal protective layer covering the terminal cover layer and formed of a third metal.

Abstract: A gate driver circuit can include a plurality of stage circuits, in which each of the plurality of stage circuits supplies a gate signal to gate lines arranged in a display panel, and includes an M node, a Q node, a QH node, a QB node, a line selector, a Q node controller, a Q node and QH node stabilizer, an inverter, a QB node stabilizer, a carry signal output circuit portion, a gate signal output circuit portion, and a Q node bootstrapper, in which the Q node bootstrapper is connected between the carry signal output circuit portion and the gate signal output circuit portion, or the gate signal output circuit portion is connected between the carry signal output circuit portion and the Q node bootstrapper.

Abstract: A semiconductor package includes: a redistribution substrate including a connection via and a redistribution layer electrically connected to each other, and a redistribution pad electrically connected to the redistribution layer by the connection via, a space pattern separating at least some of the redistribution pads from each other, a dummy metal pattern at least partially surrounded by the space pattern, and a degassing opening passing through at least one of the redistribution pad and the dummy metal pattern; a connection bump electrically connected to the redistribution pad; and a semiconductor chip on the redistribution substrate and including a connection pad electrically connected to the redistribution layer, the redistribution pad including a plurality of protrusions protruding from the same plane in directions different from each other and having a corner having a rounded shape, and the dummy metal pattern includes branch patterns each extending in directions different from one another.

Abstract: A gate driving circuit and a light emitting display apparatus comprising the same are discussed, in which a charging characteristic of a control node is improved. The gate driving circuit comprises first to mth stage circuits, wherein each of the first to mth stage circuits includes first to third control nodes, a node control circuit controlling a voltage of each of the first to third control nodes, and an output buffer circuit outputting each of a scan signal, a sense signal and a carry signal in accordance with each of the first to third control nodes, the node control circuit including a node setup circuit charging a first gate high potential voltage in the first control node in response to a first carry signal supplied from a front stage circuit.

Abstract: A semiconductor package includes a redistribution layer, a semiconductor chip disposed on the redistribution layer and an expanded layer surrounding the semiconductor chip, connection terminals on the expanded layer, and a wiring structure electrically connecting the redistribution layer to the connection terminals. Each of the connection terminal includes a seed layer, a terminal base layer including a terminal groove exposing a part of an upper surface of the seed layer on the seed layer and formed of a first metal, a terminal cover layer including a barrier portion filling the terminal groove and a cover base portion covering the barrier portion and the terminal base layer and formed of a second metal, and a terminal protective layer covering the terminal cover layer and formed of a third metal.

Abstract: A gate driving circuit and a light emitting display apparatus comprising the same are discussed, in which a charging characteristic of a control node is improved. The gate driving circuit comprises first to mth stage circuits, wherein each of the first to mth stage circuits includes first to third control nodes, a node control circuit controlling a voltage of each of the first to third control nodes, and an output buffer circuit outputting each of a scan signal, a sense signal and a carry signal in accordance with each of the first to third control nodes, the node control circuit including a node setup circuit charging a first gate high potential voltage in the first control node in response to a first carry signal supplied from a front stage circuit.