Abstract: A method for operating a Low Density Parity Check (LDPC) decoder includes assigning each symbol of a codeword as a variable node value for each of a plurality of variable nodes, performing syndrome checking on each check node based on a parity check matrix, calculating flipping function values of the variable nodes based on syndrome values of check nodes and a flipping function, dividing the flipping function values into a plurality of groups, determining a flipping function threshold value based on a group maximum value of a group among the groups, and selectively flipping a variable node value based on a comparison result of a flipping function value of corresponding variable node and the determined flipping function threshold value.

Abstract: A controller is provided to include a processor reading data from a memory device, and a decoder receiving the data and decoding the data, the data being represented with check nodes and variable nodes. The decoder includes a check unit calculating syndrome values, a calculation unit receiving the decision values of the variable nodes and calculating flipping function values, a setting unit receiving the flipping function values and generating a candidate vector by dividing the flipping function values into groups and selecting at least some maximum values from the groups, the setting unit setting a flipping function threshold value, and a flipping unit receiving the flipping function threshold value, comparing the flipping function values of the variable nodes with the flipping function threshold value, and flipping a decision value of a target variable node having a greater flipping function value than the flipping function threshold value.

Abstract: A method for operating a Low Density Parity Check (LDPC) decoder includes assigning each symbol of a codeword as a variable node value for each of a plurality of variable nodes, performing syndrome checking on each check node based on a parity check matrix, calculating flipping function values of the variable nodes based on syndrome values of check nodes and a flipping function, dividing the flipping function values into a plurality of groups, determining a flipping function threshold value based on a group maximum value of a group among the groups, and selectively flipping a variable node value based on a comparison result of a flipping function value of corresponding variable node and the determined flipping function threshold value.

Abstract: A semiconductor memory system including: a semiconductor memory device suitable for storing a codeword; and an LDPC decoder suitable for decoding the codeword to generate decoded data, wherein the LDPC decoder includes: a message passing decoding component suitable for performing a first decoding operation of decoding the codeword, and calculating the minimum value among numbers of UCNs; and an error path detection component suitable for detecting error path candidates using a tree in which each of UCNs corresponding to the minimum value is set to a root node, sorting the detected error path candidates in ascending order of maximum LLRs, resetting symbol values and LLRs of variable nodes in the error path candidates, and providing the message passing decoding unit with information on the reset symbol values and LLRs.

Abstract: A decoding method for a low density parity check (LDPC) code includes: updating a first check node, among a plurality of check nodes, by receiving, by the first check node, a bit decision and an associated first reliability value from each of a subset of variable nodes including a first variable node among a plurality of variable nodes, calculating a syndrome value and a second reliability value of the first check node based on the received bit decisions and first reliability values, and outputting the calculated syndrome value and second reliability value of the first check node to a variable node of the plurality of variable nodes but not of the subset of variable nodes; and updating the first variable node by receiving, by the first variable node, a syndrome value and a second reliability value of a second check node among the plurality of check nodes, and updating the first reliability value of the first variable node based on the syndrome value and the second reliability value of the second check node.

Abstract: A controller is provided to include a processor reading data from a memory device, and a decoder receiving the data and decoding the data, the data being represented with check nodes and variable nodes. The decoder includes a check unit calculating syndrome values, a calculation unit receiving the decision values of the variable nodes and calculating flipping function values, a setting unit receiving the flipping function values and generating a candidate vector by dividing the flipping function values into groups and selecting at least some maximum values from the groups, the setting unit setting a flipping function threshold value, and a flipping unit receiving the flipping function threshold value, comparing the flipping function values of the variable nodes with the flipping function threshold value, and flipping a decision value of a target variable node having a greater flipping function value than the flipping function threshold value.

Abstract: A semiconductor memory system including: a semiconductor memory device suitable for storing a codeword; and an LDPC decoder suitable for decoding the codeword to generate decoded data, wherein the LDPC decoder includes: a message passing decoding component suitable for performing a first decoding operation of decoding the codeword, and calculating the minimum value among numbers of UCNs; and an error path detection component suitable for detecting error path candidates using a tree in which each of UCNs corresponding to the minimum value is set to a root node, sorting the detected error path candidates in ascending order of maximum LLRs, resetting symbol values and LLRs of variable nodes in the error path candidates, and providing the message passing decoding unit with information on the reset symbol values and LLRs.

Abstract: A decoding method for a low density parity check (LDPC) code includes: updating a first check node, among a plurality of check nodes, by receiving, by the first check node, a bit decision and an associated first reliability value from each of a subset of variable nodes including a first variable node among a plurality of variable nodes, calculating a syndrome value and a second reliability value of the first check node based on the received bit decisions and first reliability values, and outputting the calculated syndrome value and second reliability value of the first check node to a variable node of the plurality of variable nodes but not of the subset of variable nodes; and updating the first variable node by receiving, by the first variable node, a syndrome value and a second reliability value of a second check node among the plurality of check nodes, and updating the first reliability value of the first variable node based on the syndrome value and the second reliability value of the second check node.

Abstract: An operating method of a controller, comprising: generating, when a first ECC decoding operation to codeword read from a semiconductor memory device according to a hard read voltage fails, an optimization information corresponding the result of the first ECC decoding operation; generating one or more quantization intervals determined by the optimization information; and performing a second ECC decoding operation to codeword read from the semiconductor memory device according to soft read voltages determined by the quantization intervals and the hard read voltage, wherein the optimization information includes: deterioration information of a memory block; ECC decoder parameter information; and constituent code parameter information.

Abstract: A processing method includes: loading, onto a substrate support of a processing chamber, a substrate having a metal oxide film deposited on a surface of the substrate; based on a predetermined temperature, controlling a temperature of coolant provided to coolant channels through the substrate support, where the predetermined temperature is less than 50 degrees Celsius; and, while controlling the temperature of the coolant based on the predetermined temperature, selectively etching the metal oxide film including: flowing molecular hydrogen into the processing chamber; and striking plasma within the processing chamber.

Abstract: An operating method of a controller includes generating a square message matrix of k×k; and generating an encoded message by encoding the square message matrix row by row through a Bose-Chadhuri-Hocquenghem (BCH) code, wherein the square message matrix includes an upper triangular matrix and a lower triangular matrix, which are symmetrical to each other with reference to zero-padding blocks included in a diagonal direction in the square message matrix, wherein the upper triangular matrix includes “?” numbers of message blocks, each of which has a size of “?+1”, and “(N??)” numbers of message blocks, each of which has a size of “?”, and wherein “?”, “?” and N have relationships represented by equations 1 and 2: ? = ? M N ? [ Equation ? ? 1 ] ? = M ? ? mod ? ? N [ Equation ? ? 2 ] where “M” represents a size of a message input from a host and “N” represents a number of message blocks forming the upper triangular matrix.

Abstract: An operation method of a controller may include encoding a first data at a first code rate such that the encoded first data is decoded by a first parity check matrix included in a variable code-rate parity check matrix and encoding a second data at a second code-rate such that the encoded second data is decoded by a second parity check matrix included in a variable code-rate parity check matrix.

Abstract: An operation method of a memory controller may include performing a first decoding operation to a message of an internal region included in a codeword received from a semiconductor memory device by using an internal parity, wherein the message and the internal parity are included in the internal region in a matrix form; and performing a second decoding operation to the internal region, to which the first decoding operation is performed, by using an outer parity of an outer region.

Abstract: An operation method of a memory controller includes: reading a second data from memory cells when a hard decision error correction decoding operation based on a first data read from the memory cells fails; calculating a LLR of each bit-data included in the first data by using the first and second data; and performing a soft decision error correction decoding operation based on the LLR, wherein the memory cells include a first and second memory cell, wherein the first data includes first-bit-data read from the first and second memory cell, wherein the second data includes second-bit-data read from the first and second memory cell, wherein the LLR is a LLR of the first-bit-data read from the first memory cell calculated based on the first bit and a second bit read from the first memory cell and a first bit and a second bit read from the second memory cell.

Abstract: An operating method of a controller, comprising: generating, when a first ECC decoding operation to codeword read from a semiconductor memory device according to a hard read voltage fails, an optimization information corresponding the result of the first ECC decoding operation; generating one or more quantization intervals determined by the optimization information; and performing a second ECC decoding operation to codeword read from the semiconductor memory device according to soft read voltages determined by the quantization intervals and the hard read voltage, wherein the optimization information includes: deterioration information of a memory block; ECC decoder parameter information; and constituent code parameter information.

Abstract: A memory system includes a memory device; and a controller suitable for encoding a message, storing the encoded message in the memory device and decoding the encoded message, wherein the controller is suitable for generating a message matrix including predetermined row codes and predetermined column codes symmetrical to the predetermined row codes, with the message or the encoded message using a block-wise concatenated Bose-Chadhuri-Hocquenghem (BCH) code with a symmetrical structure.

Abstract: An operation method of a memory controller may include performing a first decoding operation to a message of an internal region included in a codeword received from a semiconductor memory device by using an internal parity, wherein the message and the internal parity are included in the internal region in a matrix form; and performing a second decoding operation to the internal region, to which the first decoding operation is performed, by using an outer parity of an outer region.

Abstract: An electronic docking vehicle includes a vehicle body including a docking subject mechanism that docks with a first surrounding vehicle and a docking object mechanism with which a docking subject mechanism of second surrounding vehicle docks. A vehicle manipulating mechanism is provided in the vehicle body and includes a driving force generator providing a driving force to driving wheels. A steering manipulator controls a steering angle of the driving wheels. A braking manipulator generates a braking force in the driving wheels. A controller is configured to allow one vehicle to combine with the surrounding vehicle through the docking subject mechanism or the docking object mechanism.

Abstract: An operation method of a controller may include encoding a first data at a first code rate such that the encoded first data is decoded by a first parity check matrix included in a variable code-rate parity check matrix and encoding a second data at a second code-rate such that the encoded second data is decoded by a second parity check matrix included in a variable code-rate parity check matrix.

Abstract: An operation method of a memory controller includes: reading a second data from memory cells when a hard decision error correction decoding operation based on a first data read from the memory cells fails; calculating a LLR of each bit-data included in the first data by using the first and second data; and performing a soft decision error correction decoding operation based on the LLR, wherein the memory cells include a first and second memory cell, wherein the first data includes first-bit-data read from the first and second memory cell, wherein the second data includes second-bit-data read from the first and second memory cell, wherein the LLR is a LLR of the first-bit-data read from the first memory cell calculated based on the first bit and a second bit read from the first memory cell and a first bit and a second bit read from the second memory cell.