Patents by Inventor Jeong-seop SHIM

Jeong-seop SHIM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10522550
    Abstract: A semiconductor device includes a substrate including spaced-apart active regions, and device isolating regions isolating the active regions from each other, and a pillar array pattern including a plurality of pillar patterns overlapping the active regions, the plurality of pillar patterns being spaced apart from each other at an equal distance in a first direction and in a second direction intersecting the first direction, wherein the plurality of pillar patterns include first pillar patterns and second pillar patterns disposed alternatingly in the first direction and in the second direction, a shape of a horizontal cross section of the first pillar patterns being different from a shape of a horizontal cross section of the second pillar patterns.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: December 31, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki Seok Lee, Jeong Seop Shim, Mi Na Lee, Augustin Jinwoo Hong, Je Min Park, Hye Jin Seong, Seung Min Oh, Do Yeong Lee, Ji Seung Lee, Jin Seong Lee
  • Publication number: 20190088659
    Abstract: A semiconductor device includes a substrate including spaced-apart active regions, and device isolating regions isolating the active regions from each other, and a pillar array pattern including a plurality of pillar patterns overlapping the active regions, the plurality of pillar patterns being spaced apart from each other at an equal distance in a first direction and in a second direction intersecting the first direction, wherein the plurality of pillar patterns include first pillar patterns and second pillar patterns disposed alternatingly in the first direction and in the second direction, a shape of a horizontal cross section of the first pillar patterns being different from a shape of a horizontal cross section of the second pillar patterns.
    Type: Application
    Filed: November 8, 2018
    Publication date: March 21, 2019
    Inventors: Ki Seok LEE, Jeong Seop SHIM, Mi Na LEE, Augustin Jinwoo HONG, Je Min PARK, Hye Jin SEONG, Seung Min OH, Do Yeong LEE, Ji Seung LEE, Jin Seong LEE
  • Patent number: 10141316
    Abstract: A semiconductor device includes a substrate including spaced-apart active regions, and device isolating regions isolating the active regions from each other, and a pillar array pattern including a plurality of pillar patterns overlapping the active regions, the plurality of pillar patterns being spaced apart from each other at an equal distance in a first direction and in a second direction intersecting the first direction, wherein the plurality of pillar patterns include first pillar patterns and second pillar patterns disposed alternatingly in the first direction and in the second direction, a shape of a horizontal cross section of the first pillar patterns being different from a shape of a horizontal cross section of the second pillar patterns.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: November 27, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki Seok Lee, Jeong Seop Shim, Mi Na Lee, Augustin Jinwoo Hong, Je Min Park, Hye Jin Seong, Seung Min Oh, Do Yeong Lee, Ji Seung Lee, Jin Seong Lee
  • Patent number: 9934986
    Abstract: Provided is a method of forming fine patterns, which is capable of easily forming a plurality of patterns repeatedly with a fine pitch when forming patterns necessary for manufacturing a highly integrated semiconductor device exceeding a resolution limit of a photolithography process.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: April 3, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeong-seop Shim, Seok-han Park, Bum-seok Seo
  • Publication number: 20170200725
    Abstract: A semiconductor device includes a substrate including spaced-apart active regions, and device isolating regions isolating the active regions from each other, and a pillar array pattern including a plurality of pillar patterns overlapping the active regions, the plurality of pillar patterns being spaced apart from each other at an equal distance in a first direction and in a second direction intersecting the first direction, wherein the plurality of pillar patterns include first pillar patterns and second pillar patterns disposed alternatingly in the first direction and in the second direction, a shape of a horizontal cross section of the first pillar patterns being different from a shape of a horizontal cross section of the second pillar patterns.
    Type: Application
    Filed: September 26, 2016
    Publication date: July 13, 2017
    Inventors: Ki Seok LEE, Jeong Seop SHIM, Mi Na LEE, Augustin Jinwoo HONG, Je Min PARK, Hye Jin SEONG, Seung Min OH, Do Yeong LEE, Ji Seung LEE, Jin Seong LEE
  • Publication number: 20160314987
    Abstract: Provided is a method of forming fine patterns, which is capable of easily forming a plurality of patterns repeatedly with a fine pitch when forming patterns necessary for manufacturing a highly integrated semiconductor device exceeding a resolution limit of a photolithography process.
    Type: Application
    Filed: February 22, 2016
    Publication date: October 27, 2016
    Inventors: Jeong-seop SHIM, Seok-han PARK, Bum-seok SEO