Abstract: Electronic devices, displays, and methods are provided for operating an electronic display in coexistence with sensors that could be adversely impacted by the operation of the electronic display. An electronic device may include an electronic display and a sensor. The electronic display may display image content by light emission during an emission period and periodically enter a quiet period in which the light emission of the electronic display is turned off. The sensor may perform sensing operations during the quiet period without interference from the operation of the electronic display.

Abstract: An electronic display may include a first anode configured to carry a red emission signal, a second anode configured to carry a blue emission signal, a third anode configured to carry a green emission signal, and a micro-driver configured to stagger a timing of the red emission signal, the blue emission signal, and the green emission signal based on an emission clock signal to display image content on the electronic display.

Abstract: An electronic device may include an electronic display including display pixels to display an image based on compensated image data. As image data is written to a pixel in the row of pixels, capacitive coupling at a driver may lead to distortion on the driver. In particular, the capacitive coupling may cause distortion at a storage capacitor, which may lead to current droop at the pixel. The current droop may be reduced or eliminated in each pixel by performing pixel compensation. The pattern of the pixel compensation may be selected such that, over a number of subframes, an average amount of light is the same or similar to what would be emitted had pixel compensation been performed on each pixel in each subframe.

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include clock circuitry having a first plurality of logic components arranged to receive a low voltage supply, a data input signal and a clock input signal and to provide a first plurality of intermediate signals and multiple intermediate clock signals. The integrated circuit may include level converter core circuitry having voltage biasing circuitry and voltage control circuitry arranged to receive a high voltage supply, the first plurality of intermediate signals and the multiple intermediate clock signals and to provide a second plurality of intermediate signals. The integrated circuit may include latch circuitry having a second plurality of logic components arranged to receive the high voltage supply, the low voltage supply and the second plurality of intermediate signals and to provide a data output signal.

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include clock circuitry having a first plurality of logic components arranged to receive a low voltage supply, a data input signal and a clock input signal and to provide a first plurality of intermediate signals and multiple intermediate clock signals. The integrated circuit may include level converter core circuitry having voltage biasing circuitry and voltage control circuitry arranged to receive a high voltage supply, the first plurality of intermediate signals and the multiple intermediate clock signals and to provide a second plurality of intermediate signals. The integrated circuit may include latch circuitry having a second plurality of logic components arranged to receive the high voltage supply, the low voltage supply and the second plurality of intermediate signals and to provide a data output signal.