Patents by Inventor Jeoung-Mo Koo

Jeoung-Mo Koo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240243058
    Abstract: A structure includes a substrate having a frontside and a backside. A first electrode is in a first insulator layer and is adjacent to the frontside of the substrate. The first electrode is part of a redistribution layer (RDL). A second electrode is between the substrate and the first electrode. A dielectric-filled trench in the substrate is under the first electrode and the second electrode, the dielectric-filled trench may extend fully to the backside of the substrate. The structure provides a galvanic isolation that exhibits less parasitic capacitance to the substrate from the lower electrode.
    Type: Application
    Filed: January 18, 2023
    Publication date: July 18, 2024
    Inventors: Bong Woong Mun, Jeoung Mo Koo
  • Publication number: 20240153876
    Abstract: A transistor is provided. The transistor includes a substrate, a first diffusion region, a first contact structure, a second diffusion region, a second contact structure, and a gate structure. The first diffusion region is in the substrate. The first contact structure is over the substrate electrically coupling the first diffusion region. The first contact structure includes a first conductive material. The second diffusion region is in the substrate. The second contact structure is in the substrate electrically coupling the second diffusion region. The second contact structure includes a second conductive material different from the first conductive material. The gate structure is between the first contact structure and the second contact structure.
    Type: Application
    Filed: November 3, 2022
    Publication date: May 9, 2024
    Inventors: BONG WOONG MUN, ATHENA JACINTO ANTONIO, JEOUNG MO KOO
  • Patent number: 11955514
    Abstract: The embodiments herein relate to field-effect transistors (FETs) with a gate structure in a dual-depth trench isolation structure and methods of forming the same. The FET includes a substrate having an upper surface, a trench isolation structure, and a gate structure adjacent to the trench isolation structure. The trench isolation structure has a first portion having a lower surface and a second portion having a lower surface in the substrate; the lower surface of the first portion is above the lower surface of the second portion.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: April 9, 2024
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Bong Woong Mun, Jeoung Mo Koo
  • Patent number: 11862693
    Abstract: A semiconductor device may include a substrate having a source region and a drain region, and a gate arranged over the substrate and between the source region and the drain region. A first interlevel dielectric (ILD) layer may be at least partially arranged over the substrate and the gate. A conductive field plate may be arranged over the first ILD layer. At least one drain contact may extend through the first ILD layer over the drain region and may be coupled to the conductive field plate. A drain captive structure may be disposed in the first ILD layer and adjacent to the drain region, the drain captive structure having a trench comprising an air gap, wherein the drain captive structure is laterally spaced apart from sidewalls of the gate.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: January 2, 2024
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Bong Woong Mun, Jeoung Mo Koo
  • Publication number: 20230387223
    Abstract: The present disclosure generally relates to semiconductor structures for capacitive isolation, and structures incorporating the same. More particularly, the present disclosure relates to capacitive isolation structures for high voltage applications. The present disclosure also relates to methods of forming structures for capacitive isolation and the structures incorporating the same. The disclosed semiconductor structures may enable a smaller device footprint and reduced dimensions of components on an IC chip, whilst ensuring galvanic isolation between circuits.
    Type: Application
    Filed: August 8, 2023
    Publication date: November 30, 2023
    Inventors: BONG WOONG MUN, JEOUNG MO KOO
  • Publication number: 20230361173
    Abstract: A structure includes a galvanic isolation including a horizontal portion including a first redistribution layer (RDL) electrode in a first insulator layer, and a second RDL electrode in the first insulator layer laterally spaced from the first RDL electrode. An isolation break includes a trench defined in the first insulator layer between the first RDL electrode and the second RDL electrode, and at least one second insulator layer in the trench. The first insulator layer and the second insulator layer(s) are between the first RDL electrode and the second RDL electrode. The isolation may separate, for example, voltage domains having different voltage levels. A related method is also disclosed. The isolation may also include a vertical portion using the first RDL electrode and another electrode in a metal layer separated from the first RDL electrode by a plurality of interconnect dielectric layers.
    Type: Application
    Filed: July 19, 2023
    Publication date: November 9, 2023
    Inventors: Bong Woong Mun, Wanbing Yi, Juan Boon Tan, Jeoung Mo Koo
  • Publication number: 20230335580
    Abstract: An electronic device is provided, the device comprising an interposer including a dielectric material and an interconnect structure. An integrated circuit chip may be arranged over the interposer. A galvanic capacitor may be spaced from the integrated circuit chip. The galvanic capacitor having a first electrode and a second electrode. The first electrode of the galvanic capacitor may be coupled to the integrated circuit chip. A molding material may be arranged over the integrated circuit chip and the galvanic capacitor, whereby the integrated circuit chip may be spaced from the galvanic capacitor by at least a portion of the molding material.
    Type: Application
    Filed: April 19, 2022
    Publication date: October 19, 2023
    Inventors: BONG WOONG MUN, JUAN BOON TAN, SZU HUAT GOH, JEOUNG MO KOO
  • Patent number: 11791392
    Abstract: Structures for an extended-drain metal-oxide-semiconductor device and methods of forming a structure for an extended-drain metal-oxide-semiconductor device. The structure includes a substrate, a source region and a drain region in the substrate, a buffer dielectric layer positioned on the substrate adjacent to the drain region, and a gate electrode laterally positioned between the source region and the drain region. The gate electrode includes a portion that overlaps with the buffer dielectric layer, and the portion of the gate electrode includes notches.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: October 17, 2023
    Inventors: Bong Woong Mun, Upinder Singh, Jeoung Mo Koo
  • Patent number: 11791379
    Abstract: A structure includes a galvanic isolation including a horizontal portion including a first redistribution layer (RDL) electrode in a first insulator layer, and a second RDL electrode in the first insulator layer laterally spaced from the first RDL electrode. An isolation break includes a trench defined in the first insulator layer between the first RDL electrode and the second RDL electrode, and at least one second insulator layer in the trench. The first insulator layer and the second insulator layer(s) are between the first RDL electrode and the second RDL electrode. The isolation may separate, for example, voltage domains having different voltage levels. A related method is also disclosed. The isolation may also include a vertical portion using the first RDL electrode and another electrode in a metal layer separated from the first RDL electrode by a plurality of interconnect dielectric layers.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: October 17, 2023
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE LTD
    Inventors: Bong Woong Mun, Wanbing Yi, Juan Boon Tan, Jeoung Mo Koo
  • Publication number: 20230301087
    Abstract: Embodiments of the disclosure provide a circuit structure and related multi-time programmable (MTP) memory cell. The circuit structure may include a transistor having a floating gate over a semiconductor channel and a control gate on the dielectric layer. The control gate is electrically coupled to a word line. The control gate is capacitively coupled to the floating gate. A metal-insulator-metal (MIM) capacitor includes a first electrode coupled to the word line and a second electrode coupled to the floating gate of the transistor.
    Type: Application
    Filed: March 15, 2022
    Publication date: September 21, 2023
    Inventors: Bong Woong Mun, Jeoung Mo Koo
  • Patent number: 11764273
    Abstract: The present disclosure generally relates to semiconductor structures for capacitive isolation, and structures incorporating the same. More particularly, the present disclosure relates to capacitive isolation structures for high voltage applications. The present disclosure also relates to methods of forming structures for capacitive isolation and the structures incorporating the same. The disclosed semiconductor structures may enable a smaller device footprint and reduced dimensions of components on an IC chip, whilst ensuring galvanic isolation between circuits.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: September 19, 2023
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Bong Woong Mun, Jeoung Mo Koo
  • Publication number: 20230268436
    Abstract: Structures for an extended-drain metal-oxide-semiconductor device and methods of forming a structure for an extended-drain metal-oxide-semiconductor device. The structure includes a semiconductor substrate, a body well in the semiconductor substrate, a source region in the body well, a drain well in the semiconductor substrate, a drain region in the drain well, and a gate electrode laterally positioned between the source region and the drain region. The drain well includes an edge adjacent to the body well, and the edge of the drain well has a spaced relationship with the body well.
    Type: Application
    Filed: February 24, 2022
    Publication date: August 24, 2023
    Inventors: Bong Woong Mun, Upinder Singh, Jeoung Mo Koo, Huihua Jiang
  • Publication number: 20230197776
    Abstract: A structure includes a galvanic isolation including a horizontal portion including a first redistribution layer (RDL) electrode in a first insulator layer, and a second RDL electrode in the first insulator layer laterally spaced from the first RDL electrode. An isolation break includes a trench defined in the first insulator layer between the first RDL electrode and the second RDL electrode, and at least one second insulator layer in the trench. The first insulator layer and the second insulator layer(s) are between the first RDL electrode and the second RDL electrode. The isolation may separate, for example, voltage domains having different voltage levels. A related method is also disclosed. The isolation may also include a vertical portion using the first RDL electrode and another electrode in a metal layer separated from the first RDL electrode by a plurality of interconnect dielectric layers.
    Type: Application
    Filed: December 16, 2021
    Publication date: June 22, 2023
    Inventors: Bong Woong Mun, Wanbing Yi, Juan Boon Tan, Jeoung Mo Koo
  • Publication number: 20220393009
    Abstract: Structures for an extended-drain metal-oxide-semiconductor device and methods of forming a structure for an extended-drain metal-oxide-semiconductor device. The structure includes a substrate, a source region and a drain region in the substrate, a buffer dielectric layer positioned on the substrate adjacent to the drain region, and a gate electrode laterally positioned between the source region and the drain region. The gate electrode includes a portion that overlaps with the buffer dielectric layer, and the portion of the gate electrode includes notches.
    Type: Application
    Filed: June 8, 2021
    Publication date: December 8, 2022
    Inventors: Bong Woong Mun, Upinder Singh, Jeoung Mo Koo
  • Publication number: 20220384588
    Abstract: The present disclosure generally relates to semiconductor structures for capacitive isolation, and structures incorporating the same. More particularly, the present disclosure relates to capacitive isolation structures for high voltage applications. The present disclosure also relates to methods of forming structures for capacitive isolation and the structures incorporating the same. The disclosed semiconductor structures may enable a smaller device footprint and reduced dimensions of components on an IC chip, whilst ensuring galvanic isolation between circuits.
    Type: Application
    Filed: June 1, 2021
    Publication date: December 1, 2022
    Inventors: BONG WOONG MUN, JEOUNG MO KOO
  • Publication number: 20220384571
    Abstract: The embodiments herein relate to field-effect transistors (FETs) with a gate structure in a dual-depth trench isolation structure and methods of forming the same. The FET includes a substrate having an upper surface, a trench isolation structure, and a gate structure adjacent to the trench isolation structure. The trench isolation structure has a first portion having a lower surface and a second portion having a lower surface in the substrate; the lower surface of the first portion is above the lower surface of the second portion.
    Type: Application
    Filed: June 1, 2021
    Publication date: December 1, 2022
    Inventors: BONG WOONG MUN, JEOUNG MO KOO
  • Patent number: 11502193
    Abstract: Structures for an extended-drain metal-oxide-semiconductor device and methods of forming a structure for an extended-drain metal-oxide-semiconductor device. First and second source/drain regions are formed in a substrate, and a gate electrode is formed over the substrate. The gate electrode has a sidewall, and the gate electrode is laterally positioned between the first source/drain region and the second source/drain region. A buffer dielectric layer is formed that includes a first dielectric layer having a first portion positioned between the substrate and the gate electrode. The dielectric layer also has a second portion positioned on the substrate laterally between the sidewall of the gate electrode and the first source/drain region. The first portion of the dielectric layer has a first thickness, and the second portion of the first dielectric layer has a second thickness that is less than the first thickness.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: November 15, 2022
    Assignee: GlobalFoundries Singapore Pte. Ltd.
    Inventors: Bong Woong Mun, Upinder Singh, Jeoung Mo Koo
  • Patent number: 11469169
    Abstract: A capacitor is provided. The capacitor includes a first conductive layer in a first isolation region in a substrate and a plurality of dielectric layers over the first isolation region. The plurality of dielectric layers may include inter layer dielectric (ILD) and inter metal dielectric (IMD) layers. The first conductive layer is a bottom plate of the capacitor. A second conductive layer is arranged over the plurality of dielectric layers, whereby the second conductive layer is a top plate of the capacitor and at least partially overlaps with the first conductive layer.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: October 11, 2022
    Assignee: GlobalFoundries Singapore Pte. Ltd.
    Inventors: Bong Woong Mun, Jeoung Mo Koo
  • Patent number: 11456306
    Abstract: A nonvolatile memory device is provided. The nonvolatile memory device comprises a floating gate arranged over a first active region, whereby the first active region is in an active layer of a substrate. A metal-insulator-metal (MIM) capacitor may be provided laterally adjacent to the floating gate, whereby a portion of the metal-insulator-metal capacitor is in the active layer. A contact pillar may connect a first electrode of the metal-insulator-metal capacitor to the floating gate.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: September 27, 2022
    Assignee: GLOBALFOUNDRIES Singapore Ptd. Ltd.
    Inventors: Bong Woong Mun, Jeoung Mo Koo
  • Publication number: 20220165739
    Abstract: A nonvolatile memory device is provided. The nonvolatile memory device comprises a floating gate arranged over a first active region, whereby the first active region is in an active layer of a substrate. A metal-insulator-metal (MIM) capacitor may be provided laterally adjacent to the floating gate, whereby a portion of the metal-insulator-metal capacitor is in the active layer. A contact pillar may connect a first electrode of the metal-insulator-metal capacitor to the floating gate.
    Type: Application
    Filed: November 23, 2020
    Publication date: May 26, 2022
    Inventors: BONG WOONG MUN, JEOUNG MO KOO