Abstract: Pipelining is a well-known efficient technique for optimally designing high performance digital circuits. However, conventional pipelining techniques are difficult to pipeline the execution of a loop with variant iteration execution lengths in a circuit. The invention presents a new pipeline design approach, called dynamic pipelining, to design and pipeline this kind of loop in a circuit efficiently. Instead of assuming a fixed latency (or data initiation interval), the approach pipelines the loop using run-time determined latencies to achieve a high performance. The general controller architecture of it is also introduced. It consists of two interactive finite state machines to allow the pipeline datapath to execute at variant latencies. Experimental results show that the approach can obtain about 2 times speedup with acceptable area overhead.