Patents by Inventor Jer-Yuan Sheu

Jer-Yuan Sheu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9264621
    Abstract: An electronic viewfinder is configured to magnify an image and provide adjustable diopter for different observers. The electronic viewfinder includes an aperture stop, a lens group totally with positive power, and a display. The components in the electronic viewfinder are arranged sequentially between the observer and the image. The lens group is utilized to enlarge the image, and the lens group includes a first lens with positive power and a second lens with negative power. The display is for showing the image. A first planar lens is disposed between the aperture stop and the lens group. A second planar lens may be disposed between the lens group and the display. A polarizer may be arranged between the second planar lens and the lens group.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: February 16, 2016
    Assignee: ABILITY ENTERPRISES CO., LTD.
    Inventor: Jer-Yuan Sheu
  • Patent number: 8665529
    Abstract: An embodiment of this invention provides a zoom lens, which comprises, in order from an object side to an image-forming side, a first lens group having negative refractive power, a second lens group having positive refractive power, and a third lens group having positive refractive power. Further, the zoom lens satisfies the following conditions: (1) DG1/fw>0.72; (2) DG2/fw<0.72; and (3) TTL/fw<7.0, wherein fw is the focal length of the optical zoom lens at a wide-angle end, DG1 is the thickness of the first lens group, DG2 is the thickness of the second lens group, and TTL is the total thickness of the zoom lens, i.e., the distance between the object side of the first lens group and an image-forming plane of the zoom lens.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: March 4, 2014
    Assignee: Ability Enterprise Co., Ltd.
    Inventors: Huai-Yi Huang, Jer-Yuan Sheu
  • Publication number: 20120262802
    Abstract: An embodiment of this invention provides a zoom lens, which comprises, in order from an object side to an image-forming side, a first lens group having negative refractive power, a second lens group having positive refractive power, and a third lens group having positive refractive power. Further, the zoom lens satisfies the following conditions: (1) DG1/fw>0.72; (2) DG2/fw<0.72; and (3) TTL/fw<7.0, wherein fw is the focal length of the optical zoom lens at a wide-angle end, DG1 is the thickness of the first lens group, DG2 is the thickness of the second lens group, and TTL is the total thickness of the zoom lens, i.e., the distance between the object side of the first lens group and an image-forming plane of the zoom lens.
    Type: Application
    Filed: December 1, 2011
    Publication date: October 18, 2012
    Applicant: ABILITY ENTERPRISE CO., LTD.
    Inventors: HUAI-YI HUANG, JER-YUAN SHEU
  • Patent number: 6369428
    Abstract: This invention relates to the fabrication of integrated circuit devices and more particularly to a method for reducing the otherwise excessive negative TCR of low doped polysilicon load resistors in sub-micron, NMOS based, 4 transistor SRAM cells. The problem with a high negative TCR is that cell failures can occur as operating currents drop down too close to device leakage currents, when operating at cold temperatures. The key to this invention is a novel PN junction approach which causes polysilicon resistors to become electrically thicker at colder temperatures. A vertical PN junction is formed along the entire length of a polysilicon resistor and the temperature dependent space charge region of the PN junction is used for modulating the effective electrical thickness of the resistor. Consequently, the undesirable tendency for thermally activated grain boundary conduction to decrease with cold temperatures is partially compensated by a slight concurrent increase in resistor thickness.
    Type: Grant
    Filed: March 13, 2001
    Date of Patent: April 9, 2002
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Jyh-Feng Lin, Kwan-Jen Chu, Yi-Pin Shen, Jer-Yuan Sheu
  • Publication number: 20010010937
    Abstract: This invention relates to the fabrication of integrated circuit devices and more particularly to a method for reducing the otherwise excessive negative TCR of low doped polysilicon load resistors in sub-micron, NMOS based, 4 transistor SRAM cells. The problem with a high negative TCR is that cell failures can occur as operating currents drop down too close to device leakage currents, when operating at cold temperatures. The key to this invention is a novel PN junction approach which causes polysilicon resistors to become electrically thicker at colder temperatures. A vertical PN junction is formed along the entire length of a polysilicon resistor and the temperature dependent space charge region of the PN junction is used for modulating the effective electrical thickness of the resistor. Consequently, the undesirable tendency for thermally activated grain boundary conduction to decrease with cold temperatures is partially compensated by a slight concurrent increase in resistor thickness.
    Type: Application
    Filed: March 13, 2001
    Publication date: August 2, 2001
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
    Inventors: Jyh-Feng Lin, Kwan-Jen Chu, Yi-Pin Shen, Jer-Yuan Sheu
  • Patent number: 6238993
    Abstract: This invention relates to the fabrication of integrated circuit devices and more particularly to a method for reducing the otherwise excessive negative TCR of low doped polysilicon load resistors in sub-micron, NMOS based, 4 transistor SRAM cells. The problem with a high negative TCR is that cell failures can occur as operating currents drop down too close to device leakage currents, when operating at cold temperatures. The key to this invention is a novel PN junction approach which causes polysilicon resistors to become electrically thicker at colder temperatures. A vertical PN junction is formed along the entire length of a polysilicon resistor and the temperature dependent space charge region of the PN junction is used for modulating the effective electrical thickness of the resistor. Consequently, the undesirable tendency for thermally activated grain boundary conduction to decrease with cold temperatures is partially compensated by a slight concurrent increase in resistor thickness.
    Type: Grant
    Filed: April 27, 1999
    Date of Patent: May 29, 2001
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Jyh-Feng Lin, Kwan-Jen Chu, Yi-Pin Shen, Jer-Yuan Sheu
  • Patent number: 5923988
    Abstract: A process for fabricating a polycide SAC structure, for a MOSFET device, has been developed. This process features a polycide SAC structure, comprised of tungsten silicide on in situ doped polysilicon, using tungsten hexafluoride and dichlorosilane as reactants for deposition of tungsten silicide. A first thermal anneal treatment is performed prior to polycide patterning, supplying protection to exposed tungsten silicide sides, during the patterning procedure. A second thermal anneal treatment is performed after polycide patterning, and prior to a silicon oxide deposition, offering protection to the exposed top surface of tungsten silicide, during the silicon oxide deposition.
    Type: Grant
    Filed: May 15, 1998
    Date of Patent: July 13, 1999
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Hsien Cheng, Chi-Di An, Wen Jan Lin, Hung-Che Liao, Jer-Yuan Sheu