Abstract: A storage area network (“SAN”) and a system is provided. The SAN includes, a host bus adapter operationally coupled with a credit extender, wherein the credit extender receives frames from a Fibre Channel network and sends the received frames to the HBA based on buffer space available in the HBA. The HBA notifies other Fibre Channel ports of buffer space available in the credit extender. The HBA sends a signal to the credit extender notifying the credit extender of available buffer space in the HBA. The HBA includes a management port for interfacing the HBA with the credit extender.

Abstract: A method and system for transferring data from a host system to plural devices is provided. Each device may be coupled to a link having a different serial rate for accepting data from the host system. The system includes plural programmable DMA channels, which are programmed to concurrently transmit data at a rate at which the receiving devices will accept data. The method includes programming a DMA channel that can transmit data at a rate similar to the rate at which the receiving device will accept data.

Abstract: A state dependent synchronization circuit synchronizes an asynchronous input signal to a clock signal to generate a synchronous output signal. The circuit synchronizes both the leading edge and the trailing edge of the input signal and also maintains the state of the output signal at a level corresponding to the input signal when the input signal does not change. The circuit includes an input signal latch which receives the input signal and provides a latched signal which does not charge state even if the input signal subsequently changes state until the latched signal is synchronized to the clock signal. The circuit further includes a synchronizer which synchronizes the latched signal with the clock signal. The synchronizer provides feedback signals to the input signal latch to permit the input signal latch to recognize a change in the state of the input signal only after the synchronizer has synchronized the previous state of the input signal.

Abstract: A synchronization circuit synchronizes the transfer of pointer values from a transmitting circuit operating in a first clock domain to a receiving circuit operating in a second clock domain, wherein the first clock domain and the second clock domain are mutually asynchronous. An input latch operating in response to a first synchronization signal generated in the first clock domain transfers a pointer value to a latched pointer bus. The first synchronization signal is provided as an input to a synchronization section which generates a second synchronization signal in the second clock domain. The second synchronization signal enables an output latch to transfer the pointer value on the latched pointer bus to an output bus. The pointer value on the output bus is thus synchronized in the second clock domain. The second synchronization signal is then provided as an input to a synchronization section which generates the first synchronization signal in the first clock domain.