Abstract: A microcomputer is disclosed which is specifically designed for computation-intensive applications. The microcomputer contains on-chip RAM and ROM, and has peripheral ports for access of external memory and input/output functions. The central processing unit further contains two auxiliary arithmetic logic units, in parallel with one another, and which are each connected to a set address lines in a memory bus; the two auxiliary arithmetic logic units thus generate two separate memory addresses in parallel. The memory bus also contains one set of data lines, connected to the RAM and ROM, and to the central processing unit. The on-chip RAM and ROM are responsive to the two sets of address lines in time-multiplexed fashion to provide memory access via data lines twice per system clock cycle.

Abstract: A microcomputer is disclosed which is specifically designed for computation-intensive applications. The microcomputer contains on-chip RAM and ROM, and has peripheral ports for access of external memory and input/output functions. The central processing unit further contains two auxiliary arithmetic logic units, in parallel with one another, and which are each connected to a set address lines in a memory bus; the two auxiliary arithmetic logic units thus generate two separate memory addresses in parallel. The memory bus also contains one set of data lines, connected to the RAM and ROM, and to the central processing unit. The on-chip RAM and ROM are responsive to the two sets of address lines in time-multiplexed fashion to provide memory access via data lines twice per system clock cycle.

Abstract: A video display processor and video display system which overlays mobile patterns called sprites over a background. For each horizontal line the video display processor reads from an external memory data corresponding to sprites appearing on that line. This sprite data is loaded into N sprite registers. For each pixel in the horizontal line a display priority logic selects for display either the highest priority sprite or a background display if that pixel includes no sprites. If there are more than N sprites for a particular horizontal line, then an additional sprite status flag is set. The additional sprite status flag may be read by a host processor via a processor port. Reading the additional sprite status flag resets the flag. Each sprite includes a sprite number. An additional sprite number register is loaded with the sprite number of the N+1st mobile pattern on the horizontal line. This additional sprite number register may be read by a host processor via a processor port.