Patents by Inventor Jerald R. Bernacchi

Jerald R. Bernacchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Structure and method for preventing latch-up in integrated circuits
    Patent number: 5159204
    Abstract: A circuit and method for avoiding latch up in an integrated circuit in which the base-emitter junction of a parasitic bipolar transistor forming part of a parasitic SCR structure is monitored. If the forward bias of the monitored base-emitter junction approaches a predetermined value, the operation of the circuit is altered to prevent activation of the SCR.
    Type: Grant
    Filed: November 18, 1987
    Date of Patent: October 27, 1992
    Inventors: Jerald R. Bernacchi, Graham Y. Mostyn, Mohammad Yunus