Abstract: The present disclosure is generally directed to a method for driving an ultrasonic transducer. The method includes coupling a driving electrode and a ground electrode of the ultrasonic transducer to a power supply and a ground, respectively, during a first time period based on a received drive signal. The method further includes decoupling the driving electrode and the ground electrode of the ultrasonic transducer from the power supply and the ground, respectively, to float the driving electrode and the ground electrode of the ultrasonic transducer during a second time period based on the received drive signal to store a charge between the driving electrode to the ground electrode.

Abstract: A power receiver (301a, 301b, 301c, 301d, 301e, 301f) is disclosed herein. In a specific embodiment the power receiver has a first electrode (300) arranged to be electrically coupled to a body (105) of a living being, the first electrode (300) operable to receive an electrical signal via the body; and a rectifier (307) for rectifying the electrical signal into a rectified electrical signal. The rectifier (307) includes a plurality of rectifier switches and operable in a bulk biasing mode in which first selected rectifier switches of the plurality of rectifier switches are forward bulk biased. A power transmitter (201), an energy transfer apparatus (100) and a method of transmitting electrical power are also disclosed.

Abstract: An integrated circuit chip and method for EEG monitoring. In one embodiment, the integrated circuit chip includes an Analog Front End cell in communication with an electrode and a Classification Processor wherein a signal received from the electrode is processed by the Classification Engine cell and designated as seizure or non-seizure. In another embodiment, the Analog Front End cell includes an amplifier cell in communication with an electrode; and an ASPU cell in communication with the amplifier cell. In yet another embodiment, the Classification Processor includes a DBE Channel Controller cell; a Feature Extraction Engine Processor cell, and a Classification Engine cell in communication with the Feature Extraction Engine Processor cells and the DBE Channel Controller cell.

Abstract: The present disclosure is generally directed to a method for driving an ultrasonic transducer. The method includes coupling a driving electrode and a ground electrode of the ultrasonic transducer to a power supply and a ground, respectively, during a first time period based on a received drive signal. The method further includes decoupling the driving electrode and the ground electrode of the ultrasonic transducer from the power supply and the ground, respectively, to float the driving electrode and the ground electrode of the ultrasonic transducer during a second time period based on the received drive signal to store a charge between the driving electrode to the ground electrode.

Abstract: The present disclosure is generally directed to an ultrasonic transducer interface system for use within portable 2-D ultrasonic imagers and includes an on-chip adaptive beamformer and Charge-Redistribution TX (CR-TX) to provide a drive strength of up to 500 pF/channel at 5 MHz (or 10 nF at 250 kHz) while reducing the TX drive power by at least 30% compared to other ultrasonic transducer TX drivers. The ultrasonic transducer interface system can be implemented in a single chip via, for example, a complementary metal oxide semiconductor (CMOS) process.

Abstract: A SoC includes an AFE to receive a plurality of differential input channels and generate digitized data corresponding to the channels, and a classification processor configured to receive the digitized data from the AFE. The AFE includes a Dual-Channel Chopper to perform channel multiplexing of two channels while simultaneously chopping the channels, a Dual Channel Charge Recycled-AFE having an Chopper-Stabilized Capacitive-Coupled IA including bias sampling capacitors that store bias values associated with the first and second channels to enable swapping between the channel, and a DC servo loop (DSL) having a reduced setting time based on a reduction in a resistance of the pseudo-PMOS in response to engaging a system reset. The classification processor includes a Frequency-Time Division Multiplexing (FTDM) Feature Extraction (FE) engine and a Dual-Detector Architecture (D2A) classification processor.

Abstract: A SoC includes an AFE to receive a plurality of differential input channels and generate digitized data corresponding to the channels, and a classification processor configured to receive the digitized data from the AFE. The AFE includes a Dual-Channel Chopper to perform channel multiplexing of two channels while simultaneously chopping the channels, a Dual Channel Charge Recycled-AFE having an Chopper-Stabilized Capacitive-Coupled IA including bias sampling capacitors that store bias values associated with the first and second channels to enable swapping between the channel, and a DC servo loop (DSL) having a reduced setting time based on a reduction in a resistance of the pseudo-PMOS in response to engaging a system reset. The classification processor includes a Frequency-Time Division Multiplexing (FTDM) Feature Extraction (FE) engine and a Dual-Detector Architecture (D2A) classification processor.

Abstract: A radio-frequency (RF) body-coupled communications (BCC) transceiver is disclosed according to one embodiment of the present disclosure. The RF BCC transceiver includes an RF BCC transmitter and an RF BCC receiver, such that the RF BCC transmitter transmits an RF signal to the RF BCC receiver via a body area network (BAN) of a human body.

Abstract: Systems and methods for low-power single-wire communication are provided. In some embodiments, a method of operation of a transmitter to transmit a data word to a receiver using low-power single-wire communication includes receiving the data word to be transmitted to the receiver. The method also includes encoding the data word to be transmitted in a Pulsed Index Communication (PIC) format to produce a PIC data word and transmitting the PIC data word to the receiver. In this way, the transmitter may be able to transmit an increased amount of data while maintaining a simple communication protocol that uses low power and does not require a Clock-Data Recovery circuit.

Abstract: An integrated circuit chip and method for EEG monitoring. In one embodiment, the integrated circuit chip includes an Analog Front End cell in communication with an electrode and a Classification Processor wherein a signal received from the electrode is processed by the Classification Engine cell and designated as seizure or non-seizure. In another embodiment, the Analog Front End cell includes an amplifier cell in communication with an electrode; and an ASPU cell in communication with the amplifier cell. In yet another embodiment, the Classification Processor includes a DBE Channel Controller cell; a Feature Extraction Engine Processor cell, and a Classification Engine cell in communication with the Feature Extraction Engine Processor cells and the DBE Channel Controller cell.

Abstract: Systems and methods for low-power single-wire communication are provided. In some embodiments, a method of operation of a transmitter to transmit a data word to a receiver using low-power single-wire communication includes receiving the data word to be transmitted to the receiver. The method also includes encoding the data word to be transmitted in a Pulsed Index Communication (PIC) format to produce a PIC data word and transmitting the PIC data word to the receiver. In this way, the transmitter may be able to transmit an increased amount of data while maintaining a simple communication protocol that uses low power and does not require a Clock-Data Recovery circuit.

Abstract: The present disclosure is generally directed to an ultrasonic transducer interface system for use within portable 2-D ultrasonic imagers and includes an on-chip adaptive beamformer and Charge-Redistribution TX (CR-TX) to provide a drive strength of up to 500 pF/channel at 5 MHz (or 10 nF at 250 kHz) while reducing the TX drive power by at least 30% compared to other ultrasonic transducer TX drivers. The ultrasonic transducer interface system can be implemented in a single chip via, for example, a complementary metal oxide semiconductor (CMOS) process.

Abstract: A radio-frequency (RF) body-coupled communications (BCC) transceiver is disclosed according to one embodiment of the present disclosure. The RF BCC transceiver includes an RF BCC transmitter and an RF BCC receiver, such that the RF BCC transmitter transmits an RF signal to the RF BCC receiver via a body area network (BAN) of a human body.

Abstract: This disclosure is directed to a machine-based patient-specific seizure classification system. In general, an example system may comprise a non-linear SVM seizure classification system-on-chip (SoC) with multichannel EEG data acquisition and storage for epileptic patients is presented. The SoC may integrate a hardware-efficient log-linear Gaussian Basis Function engine, floating point piecewise linear natural log, and low-noise, high dynamic range readout circuits. In at least one example implementation, the SoC may consume 1.83 ?J/classification while classifying 8 channel results with an average detection rate, average false alarm rate and latency of 95.1%, 0.94% and <2 s, respectively.

Abstract: A SoC includes an AFE to receive a plurality of differential input channels and generate digitized data corresponding to the channels, and a classification processor configured to receive the digitized data from the AFE. The AFE includes a Dual-Channel Chopper to perform channel multiplexing of two channels while simultaneously chopping the channels, a Dual Channel Charge Recycled-AFE having an Chopper-Stabilized Capacitive-Coupled IA including bias sampling capacitors that store bias values associated with the first and second channels to enable swapping between the channel, and a DC servo loop (DSL) having a reduced setting time based on a reduction in a resistance of the pseudo-PMOS in response to engaging a system reset. The classification processor includes a Frequency-Time Division Multiplexing (FTDM) Feature Extraction (FE) engine and a Dual-Detector Architecture (D2A) classification processor.

Abstract: An integrated circuit chip and method for EEG monitoring. In one embodiment, the integrated circuit chip includes an Analog Front End cell in communication with an electrode and a Classification Processor wherein a signal received from the electrode is processed by the Classification Engine cell and designated as seizure or non-seizure. In another embodiment, the Analog Front End cell includes an amplifier cell in communication with an electrode; and an ASPU cell in communication with the amplifier cell. In yet another embodiment, the Classification Processor includes a DBE Channel Controller cell; a Feature Extraction Engine Processor cell, and a Classification Engine cell in communication with the Feature Extraction Engine Processor cells and the DBE Channel Controller cell.

Abstract: This disclosure is directed to a machine-based patient-specific seizure classification system. In general, an example system may comprise a non-linear SVM seizure classification system-on-chip (SoC) with multichannel EEG data acquisition and storage for epileptic patients is presented. The SoC may integrate a hardware-efficient log-linear Gaussian Basis Function engine, floating point piecewise linear natural log, and low-noise, high dynamic range readout circuits. In at least one example implementation, the SoC may consume 1.83W/classification while classifying 8 channel results with an average detection rate, average false alarm rate and latency of 95.1%, 0.94% and <2 s, respectively.

Abstract: Disclosed are a wearable monitoring apparatus and a driving method thereof. The wearable monitoring apparatus comprises: a sensor unit for measuring a biological signal from a human body, wherein the sensor unit is adhered to a skin; and a control unit for searching a location of the sensor unit, supplying power to the sensor unit, and receiving and processing the biological signal from the sensor unit, wherein the control unit is formed to be wearable.

Abstract: There is provided an inductive coupling transmitting and receiving apparatus. An inductive coupling transmitting and receiving apparatus according to an embodiment of the present invention comprises an inductive coupling transceiver transmitting and/or receiving data; an inductor connected to the inductive coupling transceiver; and a resonance compensator connected to the inductive coupling transceiver and the inductor to compensate for a change in inductance of the inductor.

Abstract: Disclosed is a rectifier circuit in order to adaptively reduce a threshold voltage of a diode module constituting the rectifier circuit using an output voltage of the rectifier circuit. A PMOS diode module flowing the forward current from an input terminal to an output terminal comprises: a first PMOS transistor including a source and a drain connected to the input terminal and the output terminal, respectively; a second PMOS transistor including a source connected to the output terminal, and a gate and a drain connected to each other; a switch connecting the gate of the first PMOS transistor to one of the output terminal and the drain of the second PMOS transistor; and a bias resistor including one terminal connected to the gate of the second PMOS transistor and another terminal to which a bias voltage is applied.