Abstract: A video dot clock generator includes a phase-locked loop (PLL) which includes a voltage controlled oscillator, a frequency divider, a phase comparator and a loop filter. The voltage controlled oscillator (VCO) is programmable to provide multiple frequency ranges for a given range of control voltages applied to the oscillator. The programming affects both the frequency range and the gain of the VCO. The phase comparator includes circuitry which simulates a predetermined minimum phase error which, when compensated for, substantially eliminates jitter in the dot clock signal. The frequency divider used in the PLL and a similar frequency divided used to generate the reference signals for the phase comparator are programmable via an internal memory which also holds programmable control signals for the VCO. The memory, in turn, may be programmed by the user to achieve desired frequency and loop again characteristics for a given application.

Abstract: A CMOS timing device having a primary oscillatory reference source, a chain of series connected bistable divider stages whose data outputs are applied to a decoder/display by way of a multiplexing network. The multiplexing network is comprised of a plurality of multiplex sections, each section having a plurality of data transmission channels or paths. Each channel includes a plurality of MOS devices of a first type connected to a common bus. All channels driving the common bus share a single MOS device of a second type which provides a complementary function with respect to the first type to establish predetermined operating voltage levels for the data logic states carried by the common bus. The data on the common bus of each multiplex section is stored in a CMOS bistable latching type flip-flop whose regenerative feedback path is MOS device controlled.