Abstract: An information handling system includes a processor, a system baseboard management controller (BMC), and a field-programmable gate array (FPGA) add-in card. The FPGA add-in card includes an FPGA programmed with accelerated function units (AFUs) to perform processing tasks for the processor. The AFUs include AFUs of a common type. A card BMC provides a temperature indication to the system BMC. The system BMC determines that a temperature of the FPGA add-in card exceeds a temperature threshold based upon the temperature indication, selects one of the common AFUs to be disabled, and directs the card BMC to disable the selected AFU. The card BMC disables the first AFU and not the second AFU in response to the direction to disable the first AFU.

Abstract: An information handling system includes a controller and first, second and third devices. The devices power-on during a power-on sequence of the information handling system. During the power-on sequence, the controller provides a first power brake signal to the first device via a first power brake line, a second power brake signal to the second device via a second power brake line, and a third power brake signal to the third device via a third power brake line. The controller removes the first power brake signal from the first power brake line. In response to an expiration of a first amount of time, the controller removes the second power brake signal from the second power brake line. In response to an expiration of a second amount of time, the controller removes the third power brake signal from the third power brake line.

Abstract: A first add-in card is connected to a second add-in card via a network communication link using a first network protocol. The first add-in card determines that a first network interface device is directly connected to a second network interface device via the network communication link, and directs that the first and second network interface devices communicate via a second network protocol based upon the first network interface device being directly connected to the second network interface device via the network communication link. The second network protocol transmits a higher proportion of data than the first network protocol.

Abstract: An information handling system includes a processor, and first and second field-programmable gate array (FPGA) add-in cards. The processor determines a configuration of the information handling system, the configuration defining architectural relationships among the first and second FPGA add-in cards and elements of the information handling system, determines that an accelerated function unit (AFU) performs its associated processing task more efficiently on the first FPGA add-in card than on the second FPGA add-in card based upon the configuration, and programs the first AFU on the first FPGA card in based upon the determination that the first AFU performs its associated processing task more efficiently on the first FPGA add-in card than on the second FPGA add-in card.

Abstract: An information handling system includes a controller and first, second and third devices. The devices power-on during a power-on sequence of the information handling system. During the power-on sequence, the controller provides a first power brake signal to the first device via a first power brake line, a second power brake signal to the second device via a second power brake line, and a third power brake signal to the third device via a third power brake line. The controller removes the first power brake signal from the first power brake line. In response to an expiration of a first amount of time, the controller removes the second power brake signal from the second power brake line. In response to an expiration of a second amount of time, the controller removes the third power brake signal from the third power brake line.

Abstract: A first add-in card is connected to a second add-in card via a network communication link using a first network protocol. The first add-in card determines that a first network interface device is directly connected to a second network interface device via the network communication link, and directs that the first and second network interface devices communicate via a second network protocol based upon the first network interface device being directly connected to the second network interface device via the network communication link. The second network protocol transmits a higher proportion of data than the first network protocol.

Abstract: An information handling system includes a processor, a system baseboard management controller (BMC), and a field-programmable gate array (FPGA) add-in card. The FPGA add-in card includes an FPGA programmed with accelerated function units (AFUs) to perform processing tasks for the processor. The AFUs include AFUs of a common type. A card BMC provides a temperature indication to the system BMC. The system BMC determines that a temperature of the FPGA add-in card exceeds a temperature threshold based upon the temperature indication, selects one of the common AFUs to be disabled, and directs the card BMC to disable the selected AFU. The card BMC disables the first AFU and not the second AFU in response to the direction to disable the first AFU.

Abstract: An information handling system includes a processor, and first and second field-programmable gate array (FPGA) add-in cards. The processor determines a configuration of the information handling system, the configuration defining architectural relationships among the first and second FPGA add-in cards and elements of the information handling system, determines that an accelerated function unit (AFU) performs its associated processing task more efficiently on the first FPGA add-in card than on the second FPGA add-in card based upon the configuration, and programs the first AFU on the first FPGA card in based upon the determination that the first AFU performs its associated processing task more efficiently on the first FPGA add-in card than on the second FPGA add-in card.