Patents by Inventor Jeremias D. Romero

Jeremias D. Romero has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9728414
    Abstract: The present method of forming an electronic structure includes providing a tantalum base layer and depositing a layer of copper on the tantalum layer, the deposition being undertaken by physical vapor deposition with the temperature of the base layer at 50.degree. C. or less, with the deposition taking place at a power level of 300 W or less.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: August 8, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventors: Wen Yu, Stephen B. Robie, Jeremias D. Romero
  • Publication number: 20140377948
    Abstract: The present method of forming an electronic structure includes providing a tantalum base layer and depositing a layer of copper on the tantalum layer, the deposition being undertaken by physical vapor deposition with the temperature of the base layer at 50.degree. C. or less, with the deposition taking place at a power level of 300 W or less.
    Type: Application
    Filed: June 24, 2014
    Publication date: December 25, 2014
    Inventors: Wen YU, Stephen B. ROBIE, Jeremias D. ROMERO
  • Publication number: 20140377949
    Abstract: The present method of forming an electronic structure includes providing a tantalum base layer and depositing a layer of copper on the tantalum layer, the deposition being undertaken by physical vapor deposition with the temperature of the base layer at 50.degree. C. or less, with the deposition taking place at a power level of 300 W or less.
    Type: Application
    Filed: June 25, 2014
    Publication date: December 25, 2014
    Inventors: Wen YU, Stephen B. ROBIE, Jeremias D. ROMERO
  • Patent number: 8791018
    Abstract: The present method of forming an electronic structure includes providing a tantalum base layer and depositing a layer of copper on the tantalum layer, the deposition being undertaken by physical vapor deposition with the temperature of the base layer at 50° C. or less, with the deposition taking place at a power level of 300 W or less.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: July 29, 2014
    Assignee: Spansion LLC
    Inventors: Wen Yu, Stephen B. Robie, Jeremias D. Romero
  • Publication number: 20080146028
    Abstract: The present method of forming an electronic structure includes providing a tantalum base layer and depositing a layer of copper on the tantalum layer, the deposition being undertaken by physical vapor deposition with the temperature of the base layer at 50° C. or less, with the deposition taking place at a power level of 300 W or less.
    Type: Application
    Filed: December 19, 2006
    Publication date: June 19, 2008
    Inventors: Wen Yu, Stephen B. Robie, Jeremias D. Romero
  • Patent number: 7169706
    Abstract: An exemplary embodiment is related to a method of using an adhesion precursor in an integrated circuit fabrication process. The method includes providing a gas of material over a dielectric material and providing a copper layer over an adhesion precursor layer. The adhesion precursor layer is formed by the gas, and the dielectric material includes an aperture.
    Type: Grant
    Filed: October 16, 2003
    Date of Patent: January 30, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sergey D. Lopatin, Paul R. Besser, Alline F. Myers, Jeremias D. Romero, Minh Q. Tran, Lu You, Pin-Chin Connie Wang
  • Patent number: 6992004
    Abstract: A method for manufacturing an integrated circuit having improved electromigration characteristics includes forming an aperture in an interlevel dielectric layer and providing a barrier layer in the aperture. The aperture is filled with a metal material and a barrier layer is provided above the metal material. An intermetallic region can be formed at an interface of the metal material and the barrier layer. The intermetallic material can be formed by implantation of species.
    Type: Grant
    Filed: July 31, 2002
    Date of Patent: January 31, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Paul R. Besser, Matthew S. Buynoski, Minh Q. Tran, Pin-Chin Connie Wang, Lu You, Sergey D. Lopatin, Jeremias D. Romero
  • Patent number: 6791081
    Abstract: A method for measuring porosity of nanoporous materials is provided using atomic force microscopy (AFM). A surface topology map with sub-atomic resolution is created using AFM wherein the pore shape and size can be determined by measuring the pores that intersect the top or fracture surface. For porous materials requiring more accurate measurements, small scan areas with slow scan speed and fine AFM tips are used and a general estimation on distribution can be made from a sample area.
    Type: Grant
    Filed: March 27, 2002
    Date of Patent: September 14, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Robert Matthew Ulfig, Suzette K. Pangrle, Alline F. Myers, Jeremias D. Romero
  • Patent number: 6518167
    Abstract: A method of forming a metal or metal nitride layer interface between a copper layer and a silicon nitride layer can include providing a metal organic gas or metal/metal nitride precursor over a copper layer, forming a metal or metal nitride layer from reactions between the metal organic gas or metal/metal nitride precursor and the copper layer, and depositing a silicon nitride layer over the metal or metal nitride layer and copper layer. The metal or metal nitride layer can provide a better interface adhesion between the silicon nitride layer and the copper layer. The metal layer can improve the interface between the copper layer and the silicon nitride layer, improving electromigration reliability and, thus, integrated circuit device performance.
    Type: Grant
    Filed: April 16, 2002
    Date of Patent: February 11, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Lu You, Matthew S. Buynoski, Paul R. Besser, Jeremias D. Romero, Pin-Chin Connie Wang, Minh Q. Tran
  • Patent number: 5713667
    Abstract: A diode is formed at the tip of a pointed portion of a probe of a scanning probe microscope. When the diode is forward biased, the current through the diode varies with the temperature of the diode. The magnitude of the current is an indication of the temperature of the tip of the probe. If the tip is scanned over a surface, a thermal map of the surface can be made and hot spots on the surface located. In some embodiments, the pointed portion of the probe is made of a semiconductor material (for example, silicon). A layer of a metal (for example, platinum) is made to contact the semiconductor material of the pointed portion only at the tip of the pointed portion, thereby forming a very small temperature sensing Schottky diode at the tip of the pointed portion.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: February 3, 1998
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Roger Alvis, Andrew N. Erickson, Ayesha R. Raheem Kizchery, Jeremias D. Romero, Bryan M. Tracy
  • Patent number: 5707484
    Abstract: A method of accurately determining the composition of a dielectric film in a semiconductor device by performing a compositional analysis on a film only portion of the semiconductor device.
    Type: Grant
    Filed: October 4, 1995
    Date of Patent: January 13, 1998
    Assignee: Advaned Micro Devices, Inc.
    Inventors: Jeremias D. Romero, Roger L. Alvis, Homi Fatemi
  • Patent number: 5290588
    Abstract: An improved process is provided for forming a multilayer structure (18) suitable for tape automated bonding thereto or for forming contacts. In the process, a first layer (12) of aluminum is formed on a substrate (10), a second layer (14) of a TiW alloy is formed on the first layer of aluminum, and a third layer (16) of gold is formed on the second layer of the TiW alloy, to which third layer of gold bonding is done. The improvement comprises annealing the second layer of the TiW alloy in an inert atmosphere at a temperature less than about 500.degree. C. for a period of time sufficient to form a film of an Al--TiW phase (20), believed to comprise TiAl.sub.3, at the interface between the first layer of aluminum and the second layer of the TiW alloy. The annealing is done prior to forming the third layer of gold on the second layer of the TiW alloy.
    Type: Grant
    Filed: December 19, 1991
    Date of Patent: March 1, 1994
    Assignee: Advanced Micro Devices, Incorporated
    Inventors: Jeremias D. Romero, Homi Fatemi, Eugene A. Delenia, Muhib M. Khan