Abstract: Disclosed is a coordinate rotation digital computer (CORDIC) having a maximum value circuit that selects a larger of the first component or the second component. A minimum value circuit selects a minimum operand that is a smaller one of the first component or the second component. Also included are N rotator stages, each corresponding to a unique one of N predetermined vectors, each of the N rotator stages having a first multiply circuit to multiply the maximum operand by a cosine coefficient of a predetermined vector to output a first rotation component, a second multiply circuit for multiplying the minimum operand by a sine coefficient of the predetermined vector to output a second rotation component, and an adder circuit for adding the first rotation component to the second rotation component to output one of N results, and a maximum value circuit for outputting a maximum one of the N results.

Abstract: Disclosed is a coordinate rotation digital computer (CORDIC) having a maximum value circuit that selects a larger of the first component or the second component. A minimum value circuit selects a minimum operand that is a smaller one of the first component or the second component. Also included are N rotator stages, each corresponding to a unique one of N predetermined vectors, each of the N rotator stages having a first multiply circuit to multiply the maximum operand by a cosine coefficient of a predetermined vector to output a first rotation component, a second multiply circuit for multiplying the minimum operand by a sine coefficient of the predetermined vector to output a second rotation component, and an adder circuit for adding the first rotation component to the second rotation component to output one of N results, and a maximum value circuit for outputting a maximum one of the N results.

Abstract: The present invention relates to synchronization circuitry that is used to synchronize an asynchronous received RF message with a transmitted RF message. In one embodiment of the present invention, the synchronization circuitry includes at least one counter, which is used to associate timing of the asynchronous received RF message with a receive count value, and associate timing of the transmitted RF message with a transmit count value. A time delay between occurrence of the receive count value and the transmit count value provides accurate timing for the start of the transmitted RF message.

Abstract: The present invention relates to synchronization circuitry that is used to synchronize an asynchronous received RF message with a transmitted RF message. In one embodiment of the present invention, the synchronization circuitry includes at least one counter, which is used to associate timing of the asynchronous received RF message with a receive count value, and associate timing of the transmitted RF message with a transmit count value. A time delay between occurrence of the receive count value and the transmit count value provides accurate timing for the start of the transmitted RF message.