Abstract: Combined display panel circuit techniques are described herein. In one or more implementations, a combined panel circuit of a display device is configured to enable functionality for both recognition of touch inputs and functionality to update images output by the display device. The combined panel circuit, for instance, may include an electrode arrangement in conductive layers that sandwiches display particles used to form images for the display device. The display particles may be manipulated under the influence of a threshold voltage applied to the electrode arrangement that is sufficient to cause the display particles to transition between states. Capacitance sensing indicative of touch inputs may occur under the influence of a different voltage that is not sufficient to manipulate the display particles. The different voltages are selectively applied at different times to update displayed images through manipulation of the display particles and sense capacitance to recognize touch inputs.

Abstract: Combined display panel circuit techniques are described herein. In one or more implementations, a combined panel circuit of a display device is configured to enable functionality for both recognition of touch inputs and functionality to update images output by the display device. The combined panel circuit, for instance, may include an electrode arrangement in conductive layers that sandwiches display particles used to form images for the display device. The display particles may be manipulated under the influence of a threshold voltage applied to the electrode arrangement that is sufficient to cause the display particles to transition between states. Capacitance sensing indicative of touch inputs may occur under the influence of a different voltage that is not sufficient to manipulate the display particles. The different voltages are selectively applied at different times to update displayed images through manipulation of the display particles and sense capacitance to recognize touch inputs.

Abstract: A system for accessing memory devices includes a processing module coupled to a set of outputs and memory operably coupled to the processing module. The memory stores operational instructions that cause the processing module to perform a plurality of operations. A first one of the plurality of operations includes utilizing a first output to provide a first data lane enable to facilitate accessing of a portion of a first memory storage location associated with a first memory address when in a first mode of operation. A second one of the plurality of operations includes utilizing the first output to provide an address bit of a second memory address to facilitate designation of a second memory storage location when in a second mode of operation.

Abstract: A method for reducing current drain in a communication device includes a step of determining when the communication device is transmitting. A next step includes lowering the current level to the receiver when communication device is not transmitting. A next step includes raising the current level to the receiver when communication device is transmitting. Changing the current level alters the linearity of the receiver. As a result, the communication device reduces power consumption while operating in a traffic channel. The system is applicable to full duplex systems such as code division multiple access (CDMA) systems.

Abstract: A system for accessing memory devices includes a processing module coupled to a set of outputs and memory operably coupled to the processing module. The memory stores operational instructions that cause the processing module to perform a plurality of operations. A first one of the plurality of operations includes utilizing a first output to provide a first data lane enable to facilitate accessing of a portion of a first memory storage location associated with a first memory address when in a first mode of operation. A second one of the plurality of operations includes utilizing the first output to provide an address bit of a second memory address to facilitate designation of a second memory storage location when in a second mode of operation.

Abstract: A method for reducing current drain in a communication device includes a step of determining when the communication device is transmitting. A next step includes lowering the current level to the receiver when communication device is not transmitting. A next step includes raising the current level to the receiver when communication device is transmitting. Changing the current level alters the linearity of the receiver. As a result, the communication device reduces power consumption while operating in a traffic channel. The system is applicable to full duplex systems such as code division multiple access (CDMA) systems.