Patents by Inventor Jeremy A. Wahl

Jeremy A. Wahl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8906802
    Abstract: One illustrative method disclosed herein includes the steps of performing a directed self-assembly process to form a DSA masking layer, performing at least one process operation to remove at least one of the features of the DSA masking layer so as to thereby define a patterned DSA masking layer with a DSA masking pattern, performing at least one process operation to form a patterned transfer masking layer having a transfer masking pattern comprised of a plurality of features that define a plurality of openings in the transfer masking layer, wherein the transfer masking pattern is the inverse of the DSA masking pattern, and performing at least one etching process through the patterned transfer masking layer on a layer of material to form a plurality of trench/via features in the layer of material.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 9, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jeremy A. Wahl, Gerard M. Schmid, Richard A. Farrell, Chanro Park
  • Patent number: 8853019
    Abstract: One method disclosed herein includes forming a layer of silicon/germanium having a germanium concentration of at least 30% on a semiconducting substrate, forming a plurality of spaced-apart trenches that extend through the layer of silicon/germanium and at least partially into the semiconducting substrate, wherein the trenches define a fin structure for the device comprised of a portion of the substrate and a portion of the layer of silicon/germanium, the portion of the layer of silicon/germanium having a first cross-sectional configuration, forming a layer of insulating material in the trenches and above the fin structure, performing an anneal process on the device so as to cause the first cross-sectional configuration of the layer of silicon/germanium to change to a second cross-sectional configuration that is different from the first cross-sectional configuration, and forming a final gate structure around at least a portion of the layer of silicon/germanium having the second cross-sectional configuration.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: October 7, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jody A. Fronheiser, Jeremy A. Wahl, Kerem Akarvardar, Ajey P. Jacob, Daniel T. Pham
  • Patent number: 8846511
    Abstract: One illustrative method disclosed herein includes forming an initial nanowire structure having an initial cross-sectional size, performing a doping diffusion process to form an N-type doped region in the initial nanowire structure and performing an etching process to remove at least a portion of the doped region and thereby define a final nanowire structure having a final cross-sectional size, wherein the final cross-sectional size is smaller than the initial cross-sectional size.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: September 30, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Nicholas V. LiCausi, Jeremy A. Wahl
  • Publication number: 20140273473
    Abstract: One illustrative method disclosed herein includes forming a patterned hard mask layer comprised of a plurality of discrete openings above a structure, wherein the patterned hard mask layer is comprised of a plurality of intersecting line-type features, forming a patterned etch mask above the patterned hard mask layer that exposes at least one, but not all, of the plurality of discrete openings, and performing at least one etching process through the patterned etch mask and the at least one exposed opening in the patterned hard mask layer to define an opening in the structure.
    Type: Application
    Filed: March 13, 2013
    Publication date: September 18, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Gerard M. Schmid, Jeremy A. Wahl, Richard A. Farrell, Chanro Park
  • Publication number: 20140273423
    Abstract: One method disclosed herein includes forming a layer of silicon/germanium having a germanium concentration of at least 30% on a semiconducting substrate, forming a plurality of spaced-apart trenches that extend through the layer of silicon/germanium and at least partially into the semiconducting substrate, wherein the trenches define a fin structure for the device comprised of a portion of the substrate and a portion of the layer of silicon/germanium, the portion of the layer of silicon/germanium having a first cross-sectional configuration, forming a layer of insulating material in the trenches and above the fin structure, performing an anneal process on the device so as to cause the first cross-sectional configuration of the layer of silicon/germanium to change to a second cross-sectional configuration that is different from the first cross-sectional configuration, and forming a final gate structure around at least a portion of the layer of silicon/germanium having the second cross-sectional configuration.
    Type: Application
    Filed: March 13, 2013
    Publication date: September 18, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Jody A. Fronheiser, Jeremy A. Wahl, Kerem Akarvardar, Ajey P. Jacob, Daniel T. Pham
  • Publication number: 20140227849
    Abstract: One illustrative method disclosed herein includes forming an initial nanowire structure having an initial cross-sectional size, performing a doping diffusion process to form an N-type doped region in the initial nanowire structure and performing an etching process to remove at least a portion of the doped region and thereby define a final nanowire structure having a final cross-sectional size, wherein the final cross-sectional size is smaller than the initial cross-sectional size.
    Type: Application
    Filed: February 12, 2013
    Publication date: August 14, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Nicholas V. LiCausi, Jeremy A. Wahl
  • Publication number: 20140203298
    Abstract: A semiconductor is formed on a (110) silicon (Si) substrate, with improved electron mobility. Embodiments include semiconductor devices having a silicon carbide (SiC) portion in the nFET channel region. An embodiment includes forming an nFET channel region and a pFET channel region in a Si substrate, such as a (110) Si substrate, and forming a silicon carbide (SiC) portion on the nFET channel region. The SiC portion may be formed by ion implantation of C followed by a recrystallization anneal or by epitaxial growth of SiC in a recess formed in the substrate. The use of SiC in the nFET channel region improves electron mobility without introducing topographical differences between NMOS and PMOS transistors.
    Type: Application
    Filed: March 19, 2014
    Publication date: July 24, 2014
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Jeremy A. WAHL, Kingsuk MAITRA
  • Patent number: 8759904
    Abstract: Electronic devices (20, 20?) of superior design flexibility that avoid channel-width quantization effects common with prior art fin-type (FIN) field effect transistors (FIN-FETS) (22) are obtained by providing multiple FIN-FETs (22) and at least one planar FET (32, 32?) on a common substrate (21), wherein the multiple FIN-FETs (22) have fins (231, 232) of at least fin heights H1 and H2, with H2<H1. The multiple FIN-FETs (22) and the at least one planar FET (32, 32?) are separated vertically as well as laterally, which aids electrical isolation therebetween. Such electrical isolation can be enhanced by forming the planar FET (32) in a semiconductor region (441) insulated from the common substrate (21).
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: June 24, 2014
    Assignee: GlobalFoundries, Inc.
    Inventors: Jeremy A. Wahl, Kingsuk Maitra
  • Patent number: 8722482
    Abstract: A semiconductor is formed on a (110) silicon (Si) substrate, with improved electron mobility. Embodiments include semiconductor devices having a silicon carbide (SiC) portion in the nFET channel region. An embodiment includes forming an nFET channel region and a pFET channel region in a Si substrate, such as a (110) Si substrate, and forming a silicon carbide (SiC) portion on the nFET channel region. The SiC portion may be formed by ion implantation of C followed by a recrystallization anneal or by epitaxial growth of SiC in a recess formed in the substrate. The use of SiC in the nFET channel region improves electron mobility without introducing topographical differences between NMOS and PMOS transistors.
    Type: Grant
    Filed: March 18, 2010
    Date of Patent: May 13, 2014
    Assignee: GlobalFoundries Inc.
    Inventors: Jeremy A. Wahl, Kingsuk Maitra
  • Patent number: 8691640
    Abstract: One illustrative method disclosed herein includes forming a plurality of trenches in a semiconductor substrate to thereby define an initial fin structure, forming sidewall spacers adjacent the initial fin structure, wherein the spacers cover a first portion of the initial fin structure and expose a second a portion of the initial fin structure, performing a doping process to form N-type doped regions in at least the exposed portion of the initial fin structure, and performing an etching process to remove at least a portion of the doped regions and thereby define a final fin structure that is vertically spaced apart from the substrate.
    Type: Grant
    Filed: January 21, 2013
    Date of Patent: April 8, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Nicholas V. LiCausi, Jeremy A. Wahl
  • Publication number: 20130196485
    Abstract: Disclosed herein are various methods for better height control of the finFET patterned fins. In one example, this invention begins by depositing or growing an oxide material, for example, silicon dioxide. This oxide material is then patterned and etched to open windows or trenches to the substrate where fins will be grown. If a common channel material is desired, it is epitaxially grown in the windows. Then, some windows are covered and one pole of fins (for example nFET) are epitaxially grown in the exposed windows. The previously masked windows are opened and the newly formed fins are masked. The alternate channel material is then grown. The masked fins are then un-masked and the oxide is recessed to allow the fins to protrude from the oxide. This invention also allows for different channel materials for NMOS and PMOS.
    Type: Application
    Filed: January 31, 2012
    Publication date: August 1, 2013
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Nicholas LiCausi, Jeremy Wahl
  • Patent number: 8481410
    Abstract: Disclosed herein are various methods for better height control of the finFET patterned fins. In one example, this invention begins by depositing or growing an oxide material, for example, silicon dioxide. This oxide material is then patterned and etched to open windows or trenches to the substrate where fins will be grown. If a common channel material is desired, it is epitaxially grown in the windows. Then, some windows are covered and one pole of fins (for example nFET) are epitaxially grown in the exposed windows. The previously masked windows are opened and the newly formed fins are masked. The alternate channel material is then grown. The masked fins are then un-masked and the oxide is recessed to allow the fins to protrude from the oxide. This invention also allows for different channel materials for NMOS and PMOS.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: July 9, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Nicholas LiCausi, Jeremy Wahl
  • Patent number: 8476137
    Abstract: Disclosed herein are methods for better variable height control of FinFET patterned fins. In one example, the method includes forming a layer on a substrate, patterning that layer to create trenches, and forming a common stack material in the trenches. Next, a pFET masking material is formed over a portion of the structure, and an nFET channel material is formed in the unmasked trenches. The pFET masking material is removed and an nFET masking material is formed over the portion of the structure that includes the nFET channel material, and a pFET channel material is formed in the unmasked trenches. Next, the unmasked patterned material is made flush with the pFET channel material, thereby creating a difference in height with the masked pattern material. Finally, the nFET masking material is removed and the patterned layer is recessed to expose pFET and nFET channel material fin structures of differing heights.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: July 2, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Nicholas LiCausi, Jeremy Wahl
  • Patent number: 8460984
    Abstract: FIN-FET ICs with adjustable FIN-FET channel widths are formed from a semiconductor layer (42). Fins (36) may be etched from the layer (42) and then some (46) locally shortened or the layer (42) may be locally thinned and then fins (46) of different fin heights etched therefrom. Either way provides fins (46) and FIN-FETs (40) with different channel widths W on the same substrate (24). Fin heights (H) are preferably shortened by implanting selected ions (A, B, C, etc.) through a mask (90, 90?, 94, 94?, 97, 97?) to locally enhance the etch rate of the layer (42) or some of the fins (36). The implant(s) (A, B, C, etc.) is desirably annealed and then differentially etched. This thins part(s) (42-i) of the layer (42) from which the fins (46) are then etched or shortens some of the fins (46) already etched from the layer (42). For silicon, germanium is a suitable implant ion.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: June 11, 2013
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Jeremy Wahl, Kingsuk Maitra
  • Publication number: 20130049136
    Abstract: Electronic devices (20, 20?) of superior design flexibility that avoid channel-width quantization effects common with prior art fin-type (FIN) field effect transistors (FIN-FETS) (22) are obtained by providing multiple FIN-FETs (22) and at least one planar FET (32, 32?) on a common substrate (21), wherein the multiple FIN-FETs (22) have fins (231, 232) of at least fin heights H1 and H2, with H2<H1. The multiple FIN-FETs (22) and the at least one planar FET (32, 32?) are separated vertically as well as laterally, which aids electrical isolation therebetween. Such electrical isolation can be enhanced by forming the planar FET (32) in a semiconductor region (441) insulated from the common substrate (21).
    Type: Application
    Filed: August 24, 2011
    Publication date: February 28, 2013
    Inventors: Jeremy A. Wahl, Kingsuk Maitra
  • Publication number: 20120313169
    Abstract: FIN-FET ICs with adjustable FIN-FET channel widths are formed from a semiconductor layer (42). Fins (36) may be etched from the layer (42) and then some (46) locally shortened or the layer (42) may be locally thinned and then fins (46) of different fin heights etched therefrom. Either way provides fins (46) and FIN-FETs (40) with different channel widths W on the same substrate (24). Fin heights (H) are preferably shortened by implanting selected ions (A, B, C, etc.) through a mask (90, 90?, 94, 94?, 97, 97?) to locally enhance the etch rate of the layer (42) or some of the fins (36). The implant(s) (A, B, C, etc.) is desirably annealed and then differentially etched. This thins part(s) (42-i) of the layer (42) from which the fins (46) are then etched or shortens some of the fins (46) already etched from the layer (42). For silicon, germanium is a suitable implant ion.
    Type: Application
    Filed: June 9, 2011
    Publication date: December 13, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Jeremy Wahl, Kingsuk Maitra
  • Publication number: 20110272775
    Abstract: A semiconductor fabrication system and method are presented. A three dimensional multilayer integrated circuit fabrication method can include forming a first device layer and forming a second device layer on top of the first device layer with minimal detrimental heat transfer to the first layer by utilizing a controlled laser layer formation annealing process. A controlled laser crystallization process can be utilized and the controlled laser can include creating an amorphous layer; defining a crystallization area in the amorphous layer, where in the crystallization area is defined to promote single crystal growth (i.e. prevent multi-crystalline growth); and applying laser to the crystallization area, wherein the laser is applied in a manner that prevents undesired heat transfer to another layer.
    Type: Application
    Filed: July 14, 2011
    Publication date: November 10, 2011
    Inventors: Eunha KIM, Jeremy WAHL, Shenqing FANG, YouSeok SUH, Kuo-Tung CHANG, Yi MA, Rinji SUGINO, Jean YANG
  • Publication number: 20110227094
    Abstract: A semiconductor is formed on a (110) silicon (Si) substrate, with improved electron mobility. Embodiments include semiconductor devices having a silicon carbide (SiC) portion in the nFET channel region. An embodiment includes forming an nFET channel region and a pFET channel region in a Si substrate, such as a (110) Si substrate, and forming a silicon carbide (SiC) portion on the nFET channel region. The SiC portion may be formed by ion implantation of C followed by a recrystallization anneal or by epitaxial growth of SiC in a recess formed in the substrate. The use of SiC in the nFET channel region improves electron mobility without introducing topographical differences between NMOS and PMOS transistors.
    Type: Application
    Filed: March 18, 2010
    Publication date: September 22, 2011
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Jeremy A. Wahl, Kingsuk Maitra
  • Patent number: 7998846
    Abstract: A semiconductor fabrication system and method are presented. A three dimensional multilayer integrated circuit fabrication method can include forming a first device layer and forming a second device layer on top of the first device layer with minimal detrimental heat transfer to the first layer by utilizing a controlled laser layer formation annealing process. A controlled laser crystallization process can be utilized and the controlled laser can include creating an amorphous layer; defining a crystallization area in the amorphous layer, where in the crystallization area is defined to promote single crystal growth (i.e. prevent multi-crystalline growth); and applying laser to the crystallization area, wherein the laser is applied in a manner that prevents undesired heat transfer to another layer.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: August 16, 2011
    Assignee: Spansion LLC
    Inventors: Eunha Kim, Jeremy Wahl, Shenqing Fang, YouSeok Suh, Kuo-Tung Chang, Yi Ma, Rinji Sugino, Jean Yang
  • Publication number: 20100065940
    Abstract: A semiconductor fabrication system and method are presented. A three dimensional multilayer integrated circuit fabrication method can include forming a first device layer and forming a second device layer on top of the first device layer with minimal detrimental heat transfer to the first layer by utilizing a controlled laser layer formation annealing process. A controlled laser crystallization process can be utilized and the controlled laser can include creating an amorphous layer; defining a crystallization area in the amorphous layer, where in the crystallization area is defined to promote single crystal growth (i.e. prevent multi-crystalline growth); and applying laser to the crystallization area, wherein the laser is applied in a manner that prevents undesired heat transfer to another layer.
    Type: Application
    Filed: September 12, 2008
    Publication date: March 18, 2010
    Inventors: Eunha KIM, Jeremy WAHL, Shenqing FANG, YouSeok SUH, Kuo-Tung CHANG, Yi MA, Rinji SUGINO, Jean YANG