Patents by Inventor Jeremy Alfred Theil
Jeremy Alfred Theil has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11244916Abstract: Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second conductive interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.Type: GrantFiled: October 16, 2019Date of Patent: February 8, 2022Assignee: Invensas Bonding Technologies, Inc.Inventors: Cyprian Emeka Uzoh, Jeremy Alfred Theil, Rajesh Katkar, Guilian Gao, Laura Wills Mirkarimi
-
Publication number: 20220020729Abstract: Dies and/or wafers are stacked and bonded in various arrangements including stacks, and may be covered with a molding to facilitate handling, packaging, and the like. In various examples, the molding may cover more or less of a stack, to facilitate connectivity with the devices of the stack, to enhance thermal management, and so forth.Type: ApplicationFiled: September 24, 2021Publication date: January 20, 2022Inventors: Guilian GAO, Cyprian Emeka UZOH, Jeremy Alfred THEIL, Belgacem HABA, Rajesh KATKAR
-
Publication number: 20220013456Abstract: Representative techniques and devices, including process steps may be employed to mitigate undesired dishing in conductive interconnect structures and erosion of dielectric bonding surfaces. For example, an embedded layer may be added to the dished or eroded surface to eliminate unwanted dishing or voids and to form a planar bonding surface. Additional techniques and devices, including process steps may be employed to form desired openings in conductive interconnect structures, where the openings can have a predetermined or desired volume relative to the volume of conductive material of the interconnect structures. Each of these techniques, devices, and processes can provide for the use of larger diameter, larger volume, or mixed-sized conductive interconnect structures at the bonding surface of bonded dies and wafers.Type: ApplicationFiled: September 27, 2021Publication date: January 13, 2022Inventors: Cyprian Emeka Uzoh, Gaius Gillman Fountain, JR., Jeremy Alfred Theil
-
Patent number: 11158573Abstract: Representative techniques and devices, including process steps may be employed to mitigate undesired dishing in conductive interconnect structures and erosion of dielectric bonding surfaces. For example, an embedded layer may be added to the dished or eroded surface to eliminate unwanted dishing or voids and to form a planar bonding surface. Additional techniques and devices, including process steps may be employed to form desired openings in conductive interconnect structures, where the openings can have a predetermined or desired volume relative to the volume of conductive material of the interconnect structures. Each of these techniques, devices, and processes can provide for the use of larger diameter, larger volume, or mixed-sized conductive interconnect structures at the bonding surface of bonded dies and wafers.Type: GrantFiled: October 18, 2019Date of Patent: October 26, 2021Assignee: Invensas Bonding Technologies, Inc.Inventors: Cyprian Emeka Uzoh, Gaius Gillman Fountain, Jr., Jeremy Alfred Theil
-
Patent number: 11158606Abstract: Dies and/or wafers are stacked and bonded in various arrangements including stacks, and may be covered with a molding to facilitate handling, packaging, and the like. In various examples, the molding may cover more or less of a stack, to facilitate connectivity with the devices of the stack, to enhance thermal management, and so forth.Type: GrantFiled: July 2, 2019Date of Patent: October 26, 2021Assignee: Invensas Bonding Technologies, Inc.Inventors: Guilian Gao, Cyprian Emeka Uzoh, Jeremy Alfred Theil, Belgacem Haba, Rajesh Katkar
-
Publication number: 20210287910Abstract: Improved bonding surfaces for microelectronics are provided. An example method of protecting a dielectric surface for direct bonding during a microelectronics fabrication process includes overfilling cavities and trenches in the dielectric surface with a temporary filler that has an approximately equal chemical and mechanical resistance to a chemical-mechanical planarization (CMP) process as the dielectric bonding surface. The CMP process is applied to the temporary filler to flatten the temporary filler down to the dielectric bonding surface. The temporary filler is then removed with an etchant that is selective to the temporary filler, but nonreactive toward the dielectric surface and toward inner surfaces of the cavities and trenches in the dielectric bonding surface. Edges of the cavities remain sharp, which minimizes oxide artifacts, strengthens the direct bond, and reduces the bonding seam.Type: ApplicationFiled: June 1, 2021Publication date: September 16, 2021Inventor: Jeremy Alfred Theil
-
Patent number: 11056348Abstract: Improved bonding surfaces for microelectronics are provided. An example method of protecting a dielectric surface for direct bonding during a microelectronics fabrication process includes overfilling cavities and trenches in the dielectric surface with a temporary filler that has an approximately equal chemical and mechanical resistance to a chemical-mechanical planarization (CMP) process as the dielectric bonding surface. The CMP process is applied to the temporary filler to flatten the temporary filler down to the dielectric bonding surface. The temporary filler is then removed with an etchant that is selective to the temporary filler, but nonreactive toward the dielectric surface and toward inner surfaces of the cavities and trenches in the dielectric bonding surface. Edges of the cavities remain sharp, which minimizes oxide artifacts, strengthens the direct bond, and reduces the bonding seam.Type: GrantFiled: April 1, 2019Date of Patent: July 6, 2021Assignee: INVENSAS BONDING TECHNOLOGIES, INC.Inventor: Jeremy Alfred Theil
-
Publication number: 20210066233Abstract: Representative implementations of techniques and methods include chemical mechanical polishing for hybrid bonding. The disclosed methods include depositing and patterning a dielectric layer on a substrate to form openings in the dielectric layer, depositing a barrier layer over the dielectric layer and within a first portion of the openings, and depositing a conductive structure over the barrier layer and within a second portion of the openings not occupied by the barrier layer, at least a portion of the conductive structure in the second portion of the openings coupled or contacting electrical circuitry within the substrate. Additionally, the conductive structure is polished to reveal portions of the barrier layer deposited over the dielectric layer and not in the second portion of the openings. Further, the barrier layer is polished with a selective polish to reveal a bonding surface on or at the dielectric layer.Type: ApplicationFiled: November 12, 2020Publication date: March 4, 2021Inventors: Gaius Gillman Fountain, JR., Chandrasekhar Mandalapu, Cyprian Emeka Uzoh, Jeremy Alfred Theil
-
Publication number: 20200381389Abstract: Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.Type: ApplicationFiled: August 18, 2020Publication date: December 3, 2020Inventors: Cyprian Emeka UZOH, Jeremy Alfred THEIL, Liang WANG, Rajesh KATKAR, Guilian GAO, Laura Wills MIRKARIMI
-
Patent number: 10840205Abstract: Methods for hybrid bonding include depositing and patterning a dielectric layer on a substrate to form openings in the dielectric layer, depositing a barrier layer over the dielectric layer and within a first portion of the openings, and depositing a conductive structure over the barrier layer and within a second portion of the openings not occupied by the barrier layer, at least a portion of the conductive structure in the second portion of the openings coupled or contacting electrical circuitry within the substrate. The conductive structure is polished to reveal portions of the barrier layer deposited over the dielectric layer and not in the second portion of the openings. Further, the barrier layer is polished with a selective polish to reveal a bonding surface on or at the dielectric layer.Type: GrantFiled: September 17, 2018Date of Patent: November 17, 2020Assignee: INVENSAS BONDING TECHNOLOGIES, INC.Inventors: Gaius Gillman Fountain, Jr., Chandrasekhar Mandalapu, Cyprian Emeka Uzoh, Jeremy Alfred Theil
-
Patent number: 10790262Abstract: Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.Type: GrantFiled: March 25, 2019Date of Patent: September 29, 2020Assignee: Invensas Bonding Technologies, Inc.Inventors: Cyprian Emeka Uzoh, Jeremy Alfred Theil, Liang Wang, Rajesh Katkar, Guilian Gao, Laura Wills Mirkarimi
-
Publication number: 20200126906Abstract: Representative techniques and devices, including process steps may be employed to mitigate undesired dishing in conductive interconnect structures and erosion of dielectric bonding surfaces. For example, an embedded layer may be added to the dished or eroded surface to eliminate unwanted dishing or voids and to form a planar bonding surface. Additional techniques and devices, including process steps may be employed to form desired openings in conductive interconnect structures, where the openings can have a predetermined or desired volume relative to the volume of conductive material of the interconnect structures. Each of these techniques, devices, and processes can provide for the use of larger diameter, larger volume, or mixed-sized conductive interconnect structures at the bonding surface of bonded dies and wafers.Type: ApplicationFiled: October 18, 2019Publication date: April 23, 2020Inventors: Cyprian Emeka UZOH, Gaius Gillman FOUNTAIN, JR., Jeremy Alfred THEIL
-
Publication number: 20200051937Abstract: Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second conductive interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.Type: ApplicationFiled: October 16, 2019Publication date: February 13, 2020Inventors: Cyprian Emeka UZOH, Jeremy Alfred THEIL, Rajesh KATKAR, Guilian GAO, Laura Wills MIRKARIMI
-
Publication number: 20200013754Abstract: Dies and/or wafers are stacked and bonded in various arrangements including stacks, and may be covered with a molding to facilitate handling, packaging, and the like. In various examples, the molding may cover more or less of a stack, to facilitate connectivity with the devices of the stack, to enhance thermal management, and so forth.Type: ApplicationFiled: July 2, 2019Publication date: January 9, 2020Inventors: Guilian GAO, Cyprian Emeka UZOH, Jeremy Alfred THEIL, Belgacem HABA, Rajesh KATKAR
-
Publication number: 20190319007Abstract: Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.Type: ApplicationFiled: March 25, 2019Publication date: October 17, 2019Inventors: Cyprian Emeka UZOH, Jeremy Alfred THEIL, Liang WANG, Rajesh KATKAR, Guilian GAO, Laura Wills MIRKARIMI
-
Publication number: 20190311911Abstract: Improved bonding surfaces for microelectronics are provided. An example method of protecting a dielectric surface for direct bonding during a microelectronics fabrication process includes overfilling cavities and trenches in the dielectric surface with a temporary filler that has an approximately equal chemical and mechanical resistance to a chemical-mechanical planarization (CMP) process as the dielectric bonding surface. The CMP process is applied to the temporary filler to flatten the temporary filler down to the dielectric bonding surface. The temporary filler is then removed with an etchant that is selective to the temporary filler, but nonreactive toward the dielectric surface and toward inner surfaces of the cavities and trenches in the dielectric bonding surface. Edges of the cavities remain sharp, which minimizes oxide artifacts, strengthens the direct bond, and reduces the bonding seam.Type: ApplicationFiled: April 1, 2019Publication date: October 10, 2019Inventor: Jeremy Alfred THEIL
-
Publication number: 20190096842Abstract: Representative implementations of techniques and methods include chemical mechanical polishing for hybrid bonding. The disclosed methods include depositing and patterning a dielectric layer on a substrate to form openings in the dielectric layer, depositing a barrier layer over the dielectric layer and within a first portion of the openings, and depositing a conductive structure over the barrier layer and within a second portion of the openings not occupied by the barrier layer, at least a portion of the conductive structure in the second portion of the openings coupled or contacting electrical circuitry within the substrate. Additionally, the conductive structure is polished to reveal portions of the barrier layer deposited over the dielectric layer and not in the second portion of the openings. Further, the barrier layer is polished with a selective polish to reveal a bonding surface on or at the dielectric layer.Type: ApplicationFiled: September 17, 2018Publication date: March 28, 2019Inventors: Gaius Gillman FOUNTAIN, JR., Chandrasekhar MANDALAPU, Cyprian Emeka UZOH, Jeremy Alfred THEIL
-
Patent number: 7152758Abstract: A dispense system stores a scented material or materials and is provided with an electrical interface that is compatible with a hand-held device. The dispense system can be connected to the hand-held device and driven with the help of the hand-held device to dispense the scented material. The dispense system can be configured to store different scented materials that can be mixed to create different scents. Logic within the hand-held device supports the mixing and dispensing of the scented materials.Type: GrantFiled: August 17, 2004Date of Patent: December 26, 2006Assignee: Avago Technologies Wireless IP (Singapore) Pte. ltd.Inventors: Ronald Shane Fazzio, Richard Ruby, Kevin Patrick Killeen, Daniel B. Roitman, Jeremy Alfred Theil