Abstract: A data storage system may connect a non-volatile memory to a quarantine module that generates a quarantine strategy in response to a pending data access request to the non-volatile memory. The quarantine strategy can proactively prescribing a plurality of status levels for physical data addresses of the non-volatile memory. A comparison of a volume of errors for the non-volatile memory to a first threshold of the quarantine strategy with the quarantine module may prompt the alteration of a first status level of the plurality of status levels for a first physical data address of the non-volatile memory, as directed by the quarantine strategy.

Abstract: A data storage system may connect a non-volatile memory to a quarantine module that generates a quarantine strategy in response to a pending data access request to the non-volatile memory. The quarantine strategy can proactively prescribing a plurality of status levels for physical data addresses of the non-volatile memory. A comparison of a volume of errors for the non-volatile memory to a first threshold of the quarantine strategy with the quarantine module may prompt the alteration of a first status level of the plurality of status levels for a first physical data address of the non-volatile memory, as directed by the quarantine strategy.

Abstract: A method of implementing a low power state within a circuit configurable to communicate at one of different communication speeds can include determining a current communication speed of the circuit and determining an inactivity duration of the circuit according to the current communication speed of the circuit. Responsive to detecting inactivity for an amount of time corresponding to the inactivity duration, the low power state can be implemented within the circuit.

Abstract: Method and apparatus for detecting timeout for packets transmitted in a packet-switched point-to-point communication system is described. In one example, timeout logic in a transmitter includes a master time counter, a first-in-first-out circuit (FIFO), difference logic, a timeout counter, and timeout detection logic. The master time counter generates a time signal, and the FIFO stores time stamps for the packets in response to the time signal. The FIFO provides a time stamp to the difference logic in response to a packet acknowledgement. The difference logic computes a time left value in response to the time stamp, the time signal, and a predefined timeout value. The timeout counter counts down from the time left value towards a zero value. The timeout detection logic produces a timeout signal in response to the timeout counter reaching the zero value.

Abstract: A packet reshuffler and a method of implementing the same is described. In one example, a digital logic circuit in a transmitter for sending packets stored in a set of buffers includes circular shift register logic, encoder logic, selection logic, and combinatorial logic. The circular shift register logic includes a plurality of registers configured to respectively store a plurality of pointers. Each of the plurality of pointers includes an address of one of the buffers, a priority value, and a type value. The encoder logic is configured to produce a plurality of sets of bits respectively associated with the plurality of pointers. The selection logic is configured to process the plurality of sets of bits to generate a shuffle entry signal associated with a selected one of said plurality of pointers. The combinatorial logic is configured to control the circular shift register logic in response to the shuffle entry signal.

Abstract: A circuit and method efficiently provide detection of corruption of data using an error correcting code (ECC). The circuit includes an ECC checker, a memory arrangement, and a detection circuit. The ECC checker generates a remainder of an ECC check of the data and an ECC value generated from an uncorrupted version of the data. The memory stores a set of values and receives a first portion of the remainder at a first address port and a second portion of the remainder at a second address port. The memory arrangement outputs a first value of the set responsive to a value of the first portion and output a second value of the set responsive to a value of the second portion. The detection circuit generates an error indication in response to the first and second values to indicate whether a single bit of the data is incorrect.

Abstract: A circuit according to an embodiment of the present invention can load data in parallel to a barrel shifter, and output data to a pipelined multiplexer stage. The multiplexer is used to direct data from predetermined barrel slots to a predetermined number of output data slots. A control logic circuit will determine which of the barrel shifter entries are the oldest, and will drive the selects of the multiplexer to direct them to the output. The second stage of the multiplexer will drive the four 16-bit outputs to generate the 64-bit user data path. Methods for implementing the embodiments of the invention are also disclosed.

Abstract: A method of outputting data from a FIFO incorporated in an integrated circuit generally determines whether input data is valid during a first clock cycle. The method then outputs data from a plurality of output barrel slots during a second clock cycle. Data is then shifted from predetermined upper barrel slots to predetermined output barrel slots during second cycle based upon a barrel count. Finally, data is shifted into the FIFO during said second cycle based upon the barrel count. A new barrel count of valid data in the FIFO can then be determined. Circuitry for implementing the embodiments of the invention is also disclosed.