Patents by Inventor Jeremy Branscome

Jeremy Branscome has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110167083
    Abstract: Embodiments of the present invention provide a hardware accelerator that assists a host database system in processing its queries. The hardware accelerator comprises special purpose processing elements that are capable of receiving database query/operation tasks in the form of machine code database instructions, execute them in hardware without software, and return the query/operation result back to the host system. For example, table and column descriptors are embedded in the machine code database instructions. For ease of installation, the hardware accelerators employ a standard interconnect, such as a PCle or HT interconnect. The processing elements implement a novel dataflow design and Inter Macro-Op Communication (IMC) data structures to execute the machine code database instructions. The hardware accelerator may also comprise a relatively large memory to enhance the hardware execution of the query/operation tasks requested.
    Type: Application
    Filed: March 15, 2011
    Publication date: July 7, 2011
    Applicant: TERADATA US, INC.
    Inventors: JEREMY BRANSCOME, MICHAEL CORWIN, LIUXI YANG, JOSEPH I. CHAMDANI
  • Publication number: 20110167055
    Abstract: Embodiments of the present invention provide a hardware accelerator that assists a host database system in processing its queries. The hardware accelerator comprises special purpose processing elements that are capable of receiving database query/operation tasks in the form of machine code database instructions, execute them in hardware without software, and return the query/operation result back to the host system. For example, table and column descriptors are embedded in the machine code database instructions. For ease of installation, the hardware accelerators employ a standard interconnect, such as a PCle or HT interconnect. The processing elements implement a novel dataflow design and Inter Macro-Op Communication (IMC) data structures to execute the machine code database instructions. The hardware accelerator may also comprise a relatively large memory to enhance the hardware execution of the query/operation tasks requested.
    Type: Application
    Filed: March 15, 2011
    Publication date: July 7, 2011
    Applicant: TERADATA US, INC.
    Inventors: JEREMY BRANSCOME, MICHAEL CORWIN, LIUXI YANG, JOSEPH I. CHAMDANI
  • Patent number: 7966343
    Abstract: Embodiments of the present invention provide one or more hardware-friendly data structures that enable efficient hardware acceleration of database operations. In particular, the present invention employs a column-store format for the database. In the database, column-groups are stored with implicit row ids (RIDs) and a RID-to-primary key column having both column-store and row-store benefits via column hopping and a heap structure for adding new data. Fixed-width column compression allow for easy hardware database processing directly on the compressed data. A global database virtual address space is utilized that allows for arithmetic derivation of any physical address of the data regardless of its location. A word compression dictionary with token compare and sort index is also provided to allow for efficient hardware-based searching of text. A tuple reconstruction process is provided as well that allows hardware to reconstruct a row by stitching together data from multiple column groups.
    Type: Grant
    Filed: April 7, 2008
    Date of Patent: June 21, 2011
    Assignee: Teradata US, Inc.
    Inventors: Liuxi Yang, Kapil Surlaker, Ravi Krishnamurthy, Michael Corwin, Jeremy Branscome, Krishnan Meiyyappan, Joseph I. Chamdani
  • Publication number: 20110099155
    Abstract: Embodiments of the present invention provide for batch and incremental loading of data into a database. In the present invention, the loader infrastructure utilizes machine code database instructions and hardware acceleration to parallelize the load operations with the I/O operations. A large, hardware accelerator memory is used as staging cache for the load process. The load process also comprises an index profiling phase that enables balanced partitioning of the created indexes to allow for pipelined load. The online incremental loading process may also be performed while serving queries.
    Type: Application
    Filed: January 4, 2011
    Publication date: April 28, 2011
    Applicant: TERADATA US INC.
    Inventors: James Shau, Krishnan Meiyyappan, Hung Tran, Ravi Krishnamurthy, Kapil Surlaker, Jeremy Branscome, Joseph I. Chamdani
  • Patent number: 7908259
    Abstract: Embodiments of the present invention provide a hardware accelerator that assists a host database system in processing its queries. The hardware accelerator comprises special purpose processing elements that are capable of receiving database query/operation tasks in the form of machine code database instructions, execute them in hardware without software, and return the query/operation result back to the host system. For example, table and column descriptors are embedded in the machine code database instructions. For ease of installation, the hardware accelerators employ a standard interconnect, such as a PCIe or HT interconnect. The processing elements implement a novel dataflow design and Inter Macro-Op Communication (IMC) data structures to execute the machine code database instructions. The hardware accelerator may also comprise a relatively large memory to enhance the hardware execution of the query/operation tasks requested.
    Type: Grant
    Filed: August 27, 2007
    Date of Patent: March 15, 2011
    Assignee: Teradata US, Inc.
    Inventors: Jeremy Branscome, Michael Corwin, Liuxi Yang, Joseph I. Chamdani
  • Patent number: 7895151
    Abstract: Embodiments of the present invention provide for batch and incremental loading of data into a database. In the present invention, the loader infrastructure utilizes machine code database instructions and hardware acceleration to parallelize the load operations with the I/O operations. A large, hardware accelerator memory is used as staging cache for the load process. The load process also comprises an index profiling phase that enables balanced partitioning of the created indexes to allow for pipelined load. The online incremental loading process may also be performed while serving queries.
    Type: Grant
    Filed: June 23, 2008
    Date of Patent: February 22, 2011
    Assignee: Teradata US, Inc.
    Inventors: James Shau, Krishnan Meiyyappan, Hung Tran, Ravi Krishnamurthy, Kapil Surlaker, Jeremy Branscome, Joseph I Chamdani
  • Publication number: 20100082895
    Abstract: A multi-level content addressable memory (CAM) architecture compresses out much of the redundancy encountered in the search space of a single CAM, particularly for flow-based lookups in a network. Destination and source address may be associated with internal equivalence classes independently in one level of the multi-level CAM architecture, while flow-specific properties linking arbitrary classes of the destination and source addresses may be applied in a later level of the multi-level CAM.
    Type: Application
    Filed: September 25, 2009
    Publication date: April 1, 2010
    Inventors: Jeremy Branscome, Michael Corwin
  • Publication number: 20100005077
    Abstract: Embodiments of the present invention generate and optimize query plans that are at least partially executable in hardware. Upon receiving a query, the query is rewritten and optimized with a bias for hardware execution of fragments of the query. A template-based algorithm may be employed for transforming a query into fragments and then into query tasks. The various query tasks can then be routed to either a hardware accelerator, a software module, or sent back to a database management system for execution. For those tasks routed to the hardware accelerator, the query tasks are compiled into machine code database instructions.
    Type: Application
    Filed: July 7, 2008
    Publication date: January 7, 2010
    Applicant: Kickfire, Inc.
    Inventors: Ravi Krishnamurthy, Chi-Young Ku, James Shau, Chun Zhang, Kapil Surlaker, Jeremy Branscome, Michael Corwin, Joseph I. Chamdani
  • Publication number: 20090319550
    Abstract: Embodiments of the present invention provide for batch and incremental loading of data into a database. In the present invention, the loader infrastructure utilizes machine code database instructions and hardware acceleration to parallelize the load operations with the I/O operations. A large, hardware accelerator memory is used as staging cache for the load process. The load process also comprises an index profiling phase that enables balanced partitioning of the created indexes to allow for pipelined load. The online incremental loading process may also be performed while serving queries.
    Type: Application
    Filed: June 23, 2008
    Publication date: December 24, 2009
    Applicant: Kickfire, Inc.
    Inventors: James Shau, Krishnan Meiyyappan, Hung Tran, Ravi Krishnamurthy, Kapil Surlaker, Jeremy Branscome, Joseph I. Chamdani
  • Publication number: 20090319486
    Abstract: Embodiments of the present invention provide fine grain concurrency control for transactions in the presence of database updates. During operations, each transaction is assigned a snapshot version number or SVN. A SVN refers to a historical snapshot of the database that can be created periodically or on demand. Transactions are thus tied to a particular SVN, such as, when the transaction was created. Queries belonging to the transactions can access data that is consistent as of a point in time, for example, corresponding to the latest SVN when the transaction was created. At various times, data from the database stored in a memory can be updated using the snapshot data corresponding to a SVN. When a transaction is committed, a snapshot of the database with a new SVN is created based on the data modified by the transaction and the snapshot is synchronized to the memory.
    Type: Application
    Filed: June 23, 2008
    Publication date: December 24, 2009
    Applicant: Kickfire, Inc.
    Inventors: Kapil Surlaker, Ravi Krishnamurthy, Krishnan Meiyyappan, Alan Beck, Hung Tran, Jeremy Branscome, Joseph I. Chamdani
  • Patent number: 7606968
    Abstract: A multi-level content addressable memory (CAM) architecture compresses out much of the redundancy encountered in the search space of a single CAM, particularly for flow-based lookups in a network. Destination and source address may be associated with internal equivalence classes independently in one level of the multi-level CAM architecture, while flow-specific properties linking arbitrary classes of the destination and source addresses may be applied in a later level of the multi-level CAM.
    Type: Grant
    Filed: May 8, 2006
    Date of Patent: October 20, 2009
    Assignee: McData Corporation
    Inventors: Jeremy Branscome, Michael Corwin
  • Publication number: 20090254532
    Abstract: Embodiments of the present invention provide one or more hardware-friendly data structures that enable efficient hardware acceleration of database operations. In particular, the present invention employs a column-store format for the database. In the database, column-groups are stored with implicit row ids (RIDs) and a RID-to-primary key column having both column-store and row-store benefits via column hopping and a heap structure for adding new data. Fixed-width column compression allow for easy hardware database processing directly on the compressed data. A global database virtual address space is utilized that allows for arithmetic derivation of any physical address of the data regardless of its location. A word compression dictionary with token compare and sort index is also provided to allow for efficient hardware-based searching of text. A tuple reconstruction process is provided as well that allows hardware to reconstruct a row by stitching together data from multiple column groups.
    Type: Application
    Filed: April 7, 2008
    Publication date: October 8, 2009
    Inventors: Liuxi Yang, Kapil Surlaker, Ravi Krishnamurthy, Michael Corwin, Jeremy Branscome, Krishnan Meiyyappan, Joseph I. Chamdani
  • Publication number: 20090254774
    Abstract: Embodiments of the present invention provide a run-time scheduler that schedules tasks for database queries on one or more execution resources in a dataflow fashion. In some embodiments, the run-time scheduler may comprise a task manager, a memory manager, and hardware resource manager. When a query is received by a host database management system, a query plan is created for that query. The query plan splits a query into various fragments. These fragments are further compiled into a directed acyclic graph of tasks. Unlike conventional scheduling, the dependency arc in the directed acyclic graph is based on page resources. Tasks may comprise machine code that may be executed by hardware to perform portions of the query. These tasks may also be performed in software or relate to I/O.
    Type: Application
    Filed: April 7, 2008
    Publication date: October 8, 2009
    Applicant: Kickfire, Inc.
    Inventors: Joseph I. Chamdani, Alan Beck, Hareesh Boinepelli, Jim Crowley, Ravi Krishnamurthy, Jeremy Branscome
  • Publication number: 20090254516
    Abstract: Embodiments of the present invention provide hardware-friendly indexing of databases. In particular, forward and reverse indexing are utilized to allow for easy traversal of primary key to foreign key relationships. A novel structure known as a hit list also allows for easy scanning of various indexes in hardware. Group indexing is provided for flexible support of complex group key definition, such as for date range indexing and text indexing. A Replicated Reordered Column (RRC) may also be added to the group index to convert random I/O pattern into sequential I/O of only needed column elements.
    Type: Application
    Filed: April 7, 2008
    Publication date: October 8, 2009
    Inventors: Krishnan Meiyyappan, Liuxi Yang, Jeremy Branscome, Michael Corwin, Ravi Krishnamurthy, Kapil Surlaker, James Shau, Joseph I. Chamdani
  • Publication number: 20080189251
    Abstract: Embodiments of the present invention provide processing elements that are capable of performing high level database operations in hardware based on machine code instructions. These processing elements employ a dataflow architecture that operates on data in hardware without interruption or software. A scanning/indexing processing element may comprise logic that analyze database column groups stored in local memory, perform parallel field extraction and comparison, and generates a list of row pointers (row ids or RIDs) referencing those rows whose value(s) satisfy an applied predicate. The scanning/indexing processing may also be used to project database column groups, search and join index structures, and manipulate in-flight metadata flows, composing, merging, reducing, and modifying multi-dimensional lists of intermediate and final results.
    Type: Application
    Filed: August 27, 2007
    Publication date: August 7, 2008
    Inventors: Jeremy Branscome, Michael Corwin, Liuxi Yang, James Shau, Ravi Krishnamurthy, Joseph I. Chamdani
  • Publication number: 20080189252
    Abstract: Embodiments of the present invention provide a hardware accelerator that assists a host database system in processing its queries. The hardware accelerator comprises special purpose processing elements that are capable of receiving database query/operation tasks in the form of machine code database instructions, execute them in hardware without software, and return the query/operation result back to the host system. For example, table and column descriptors are embedded in the machine code database instructions. For ease of installation, the hardware accelerators employ a standard interconnect, such as a PCIe or HT interconnect. The processing elements implement a novel dataflow design and Inter Macro-Op Communication (IMC) data structures to execute the machine code database instructions. The hardware accelerator may also comprise a relatively large memory to enhance the hardware execution of the query/operation tasks requested.
    Type: Application
    Filed: August 27, 2007
    Publication date: August 7, 2008
    Inventors: Jeremy Branscome, Michael Corwin, Liuxi Yang, Joseph I. Chamdani
  • Publication number: 20080183688
    Abstract: Embodiments of the present invention provide a database system that is optimized by using hardware acceleration. The system may be implemented in several variations to accommodate a wide range of queries and database sizes. In some embodiments, the system may comprise a host system that is coupled to one or more hardware accelerator components. The host system may execute software or provide an interface for receiving queries. The host system analyzes and parses these queries into tasks. The host system may then select some of the tasks and translate them into machine code instructions, which are executed by one or more hardware accelerator components. The tasks executed by hardware accelerators are generally those tasks that may be repetitive or processing intensive. Such tasks may include, for example, indexing, searching, sorting, table scanning, record filtering, and the like.
    Type: Application
    Filed: August 27, 2007
    Publication date: July 31, 2008
    Inventors: Joseph I. Chamdani, Raj Cherabuddi, Michael Corwin, Jeremy Branscome, Liuxi Yang, Ravi Krishnamurthy
  • Publication number: 20070260814
    Abstract: A multi-level content addressable memory (CAM) architecture compresses out much of the redundancy encountered in the search space of a single CAM, particularly for flow-based lookups in a network. Destination and source address may be associated with internal equivalence classes independently in one level of the multi-level CAM architecture, while flow-specific properties linking arbitrary classes of the destination and source addresses may be applied in a later level of the multi-level CAM.
    Type: Application
    Filed: May 8, 2006
    Publication date: November 8, 2007
    Inventors: Jeremy Branscome, Michael Corwin