Abstract: A machine learning hardware accelerator architecture and associated techniques are disclosed. The architecture features multiple memory banks of very wide SRAM that may be concurrently accessed by a large number of parallel operational units. Each operational unit supports an instruction set specific to machine learning, including optimizations for performing tensor operations and convolutions. Optimized addressing, an optimized shift reader and variations on a multicast network that permutes and copies data and associates with an operational unit that support those operations are also disclosed.

Abstract: A machine learning hardware accelerator architecture and associated techniques are disclosed. The architecture features multiple memory banks of very wide SRAM that may be concurrently accessed by a large number of parallel operational units. Each operational unit supports an instruction set specific to machine learning, including optimizations for performing tensor operations and convolutions. Optimized addressing, an optimized shift reader and variations on a multicast network that permutes and copies data and associates with an operational unit that support those operations are also disclosed.

Abstract: An architecture and associated techniques of an apparatus for hardware accelerated machine learning are disclosed. The architecture features multiple memory banks storing tensor data. The tensor data may be concurrently fetched by a number of execution units working in parallel. Each operational unit supports an instruction set specific to certain primitive operations for machine learning. An instruction decoder is employed to decode a machine learning instruction and reveal one or more of the primitive operations to be performed by the execution units, as well as the memory addresses of the operands of the primitive operations as stored in the memory banks. The primitive operations, upon performed or executed by the execution units, may generate some output that can be saved into the memory banks. The fetching of the operands and the saving of the output may involve permutation and duplication of the data elements involved.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for implementing a zero knowledge prover are disclosed. In one aspect, a method includes the actions of accessing an instruction set of a processor. The actions include generating a representation of a computing instruction using Boolean logic operations. The actions include assigning a polynomial constraint of a group of polynomial constraints to each Boolean logic operation. The actions include providing, to the processor, an executable program that includes various computing instructions and a request to execute the executable program. The actions include monitoring a value of a register of the processor. The actions include determining whether the value of the register complies with polynomial constraints of the group of polynomial constraints that correspond to instructions performed on the register.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for implementing a zero knowledge prover are disclosed. In one aspect, a method includes the actions of executing a software program. The method further includes storing an execution trace that includes, for each address in memory, a value at each clock cycle during execution of the software program. The method further includes generating a sorted execution trace by sorting the execution trace. The method further includes determining a constraint for given values in the memory at adjacent clock cycles. The method further includes determining whether the sorted execution trace complies with the constraint and whether the sorted execution trace is a permutation of the execution trace. The method further includes providing, for output, data indicating whether the software program executed correctly while preventing outputting data included in the execution trace or the sorted execution trace.

Abstract: In one embodiment, a system to deterministically transfer partitions of contiguous computer readable data in constant time includes a computer readable memory and a modulo address generator. The computer readable memory is organized into D banks, to contain contiguous data including a plurality of data elements of size M which are constituent data elements of a vector with N data elements, the data elements to start at an offset address O. The modulo address generator is to generate the addresses of the data elements of a vector with i data elements stored in the computer readable memory, the modulo address generator including at least one forward permutaton to permute data elements with addresses of the form O+M*i where 0<=i<N. Other embodiments are described and claimed.

Abstract: A machine learning hardware accelerator architecture and associated techniques are disclosed. The architecture features multiple memory banks of very wide SRAM that may be concurrently accessed by a large number of parallel operational units. Each operational unit supports an instruction set specific to machine learning, including optimizations for performing tensor operations and convolutions. Optimized addressing, an optimized shift reader and variations on a multicast network that permutes and copies data and associates with an operational unit that support those operations are also disclosed.

Abstract: In one embodiment, a system to deterministically transfer partitions of contiguous computer readable data in constant time includes a computer readable memory and a modulo address generator. The computer readable memory is organized into D banks, to contain contiguous data including a plurality of data elements of size M which are constituent data elements of a vector with N data elements, the data elements to start at an offset address O. The modulo address generator is to generate the addresses of the data elements of a vector with i data elements stored in the computer readable memory, the modulo address generator including at least one forward permutaton to permute data elements with addresses of the form O+M*i where 0<=i<N.

Abstract: A machine learning hardware accelerator architecture and associated techniques are disclosed. The architecture features multiple memory banks of very wide SRAM that may be concurrently accessed by a large number of parallel operational units. Each operational unit supports an instruction set specific to machine learning, including optimizations for performing tensor operations and convolutions. Optimized addressing, an optimized shift reader and variations on a multicast network that permutes and copies data and associates with an operational unit that support those operations are also disclosed.

Abstract: Neural network specific hardware acceleration optimizations are disclosed, including an optimized multicast network and an optimized DRAM transfer unit to perform in constant or linear time. The multicast network is a set of switch nodes organized into layers and configured to operate as a Beneš network. Configuration data may be accessed by all switch nodes in the network. Each layer is configured to perform a Beneš network transformation of the -previous layer within a computer instruction. Since the computer instructions are pipelined, the entire network of switch nodes may be configured in constant or linear time. Similarly a DRAM transfer unit configured to access memory in strides organizes memory into banks indexed by prime or relatively prime number amounts. The index value is selected as not to cause memory address collisions. Upon receiving a memory specification, the DRAM transfer unit may calculate out strides thereby accessing an entire tile of a tensor in constant or linear time.

Abstract: An architecture and associated techniques of an apparatus for hardware accelerated machine learning are disclosed. The architecture features multiple memory banks storing tensor data. The tensor data may be concurrently fetched by a number of execution units working in parallel. Each operational unit supports an instruction set specific to certain primitive operations for machine learning. An instruction decoder is employed to decode a machine learning instruction and reveal one or more of the primitive operations to be performed by the execution units, as well as the memory addresses of the operands of the primitive operations as stored in the memory banks. The primitive operations, upon performed or executed by the execution units, may generate some output that can be saved into the memory banks. The fetching of the operands and the saving of the output may involve permutation and duplication of the data elements involved.

Abstract: An architecture and associated techniques of an apparatus for hardware accelerated machine learning are disclosed. The architecture features multiple memory banks storing tensor data. The tensor data may be concurrently fetched by a number of execution units working in parallel. Each operational unit supports an instruction set specific to certain primitive operations for machine learning. An instruction decoder is employed to decode a machine learning instruction and reveal one or more of the primitive operations to be performed by the execution units, as well as the memory addresses of the operands of the primitive operations as stored in the memory banks. The primitive operations, upon performed or executed by the execution units, may generate some output that can be saved into the memory banks. The fetching of the operands and the saving of the output may involve permutation and duplication of the data elements involved.

Abstract: Techniques to preprocess tensor operations prior to code generation to optimize compilation are disclosed. A computer readable representation of a linear algebra or tensor operation is received. A code transformation software component performs transformations include output reduction and fraction removal. The result is a set of linear equations of a single variable with integer coefficients. Such a set lends itself to more efficient code generation during compilation by a code generation software component. Use cases disclosed include targeting a machine learning hardware accelerator, receiving code in the form of an intermediate language generated by a cross-compiler with multiple front ends supporting multiple programming languages, and cloud deployment and execution scenarios.

Abstract: The Prefix Burrows-Wheeler Transform (“PWBT”) is described to provide data operations on data sets even if the data set has been compressed. Techniques to set up a PWBT, including an offset table and a prefix table, and techniques to apply data operations on data sets transformed by PWBT are also described. Data operations include k-Mer substring search. General applications of techniques using PWBT, such as plagiarism searches and open source clearance, are described. Bioinformatics applications of the PWBT, such as genomic analysis and genomic tagging, are also described.

Abstract: A facility for performing employing multiple frequencies in a secure distributed hierarchical convergence network is described. The facility receives a signal in a first frequency, converts the received signal to an internal representation, applies a business rule to the converted signal, and, when the business rule indicates that the signal should be transmitted in a second frequency, causes the internal representation of the signal to be translated to a second frequency and transmitted in the second frequency.

Abstract: A protocol circuit layer is described. The protocol circuit layer may employ a routing layer to determine optimal routes when establishing a circuit. The circuit layer may employ a link layer to send data packets over links to other network nodes. A naming layer may employ circuits to establish a distributed database of associations between network node addresses and their network locations.

Abstract: Embodiments communicate messages between mobile devices and destination devices. An exemplary embodiment includes a first border server operable to establish a first communication connection to the mobile device over a first network operating under a first protocol, a second border server operable to establish a second communication connection to the mobile device over a second network operating under a second protocol, and a transport management server communicatively coupled to the first border server and the second border server, and operable to establish a third communication connection to the destination device over a third network operating under a third protocol. The first protocol is configured to communicate a first encapsulated portion of the message. The second protocol is configured to communicate a second encapsulated portion of the message. The third protocol is configured to communicate the first encapsulated portion of the message and the second encapsulated portion of the message.

Abstract: A protocol circuit layer is described. The protocol circuit layer may employ a routing layer to determine optimal routes when establishing a circuit. The circuit layer may employ a link layer to send data packets over links to other network nodes. A naming layer may employ circuits to establish a distributed database of associations between network node addresses and their network locations.

Abstract: A facility for performing employing multiple frequencies in a secure distributed hierarchical convergence network is described. The facility receives a signal in a first frequency, converts the received signal to an internal representation, applies a business rule to the converted signal, and, when the business rule indicates that the signal should be transmitted in a second frequency, causes the internal representation of the signal to be translated to a second frequency and transmitted in the second frequency.

Abstract: A facility for congestion management and latency prediction is described. In various embodiments, the facility sums a series of fractional transmission delays wherein each fractional transmission delay is measured as a probability of a failed transmission attempt multiplied by the cost of the failed transmission attempt, and provides the sum.