Abstract: A phase locked loop (PLL) device is configurable in an analog phase locked loop and a hybrid analog-digital phase locked loop. In an analog mode, at least a phase detector, an analog loop filter, and a voltage controlled oscillator (VCO), are connected to form an analog loop. In a digital mode, at least the phase detector, the voltage controlled oscillator (VCO), a time to digital converter (TDC), a digital loop filter and a digital to analog converter (DAC) are connected to form the hybrid digital-analog loop.

Abstract: Exemplary embodiments are directed to wireless power. A method may comprise receiving wireless power with a receiver and charging an accumulator with energy from the received wireless power. The method may further include conveying energy from the accumulator to an energy storage device upon a charging level of the accumulator reaching a threshold level.

Abstract: A method of harmonic selection for mixing with a received signal includes receiving a radio frequency (RF) signal and determining a variable gain setting from among a plurality of gain settings or from a range of gain settings. The variable gain setting is based on the RF signal. The method further includes selecting a harmonic to provide to an input of a mixer to generate an output signal. A baseband signal or an intermediate frequency signal is generated from the output signal. The harmonic is selected based on the variable gain setting. An apparatus includes a harmonic selector that is configured to generate an indication of a selected harmonic. The harmonic is selected based on a variable gain setting determined from among a plurality of gain settings or from a range of gain settings. Based on the selected harmonic, a mixer generates an output signal. A baseband signal or an intermediate signal is generated from the output signal.

Abstract: Exemplary embodiments are directed to energy storage device security. An energy storage device may include at least one energy storage cell and a controller. The controller may be configured to request device identification data from an electronic device coupled to the energy storage device and compare the device identification data to device identification data stored in the energy storage device. The controller may be further configured to enable energy to be conveyed from the at least one energy storage cell to the electronic device if the device identification matches the stored device identification data.

Abstract: A method of harmonic selection for mixing with a received signal includes receiving a radio frequency (RF) signal and determining a variable gain setting from among a plurality of gain settings or from a range of gain settings. The variable gain setting is based on the RF signal. The method further includes selecting a harmonic to provide to an input of a mixer to generate an output signal. A baseband signal or an intermediate frequency signal is generated from the output signal. The harmonic is selected based on the variable gain setting. An apparatus includes a harmonic selector that is configured to generate an indication of a selected harmonic. The harmonic is selected based on a variable gain setting determined from among a plurality of gain settings or from a range of gain settings. Based on the selected harmonic, a mixer generates an output signal. A baseband signal or an intermediate signal is generated from the output signal.

Abstract: Exemplary embodiments are directed to selective wireless power transfer. A method may include transferring wireless power to at least one electronic device while varying at least one parameter of the wireless power transfer according to a wireless power transfer scenario.

Abstract: A method of performing modulation of a data signal at a phase-locked loop (PLL) includes generating, at an upper frequency port of the PLL, a digital loop signal based at least in part on the data signal. The method further includes differentiating the digital loop signal to generate a digital input signal and converting the digital input signal to an analog current signal. A first feedback signal is generated based on the analog current signal. The method further includes generating, at a lower frequency port of the PLL, a second feedback signal based on the first feedback signal and further based on the data signal. According to further embodiments, apparatuses and a computer-readable medium are disclosed.

Abstract: A method of performing modulation of a data signal at a phase-locked loop (PLL) includes generating, at an upper frequency port of the PLL, a digital loop signal based at least in part on the data signal. The method further includes differentiating the digital loop signal to generate a digital input signal and converting the digital input signal to an analog current signal. A first feedback signal is generated based on the analog current signal. The method further includes generating, at a lower frequency port of the PLL, a second feedback signal based on the first feedback signal and further based on the data signal. According to further embodiments, apparatuses and a computer-readable medium are disclosed.

Abstract: A phase locked loop (PLL) device includes a digital differentiator configured to differentiate a digital loop signal to at least partially compensate for the integration of an analog current signal by an analog integrator. A digital to analog converter (DAC) includes a current source output stage that generates the analog current signal based on an digital input signal. The analog integrator integrates the analog current signal to generate a voltage control signal for controlling a voltage controlled oscillator (VCO).

Abstract: Switches with connected bulk for improved switching performance and bias resistors for even voltage distribution to improve reliability are described. In an exemplary design, a switch may include a plurality of transistors coupled in a stack and at least one resistor coupled to at least one intermediate node in the stack. The transistors may have (i) a first voltage applied to a first transistor in the stack and (ii) a second voltage that is lower than the first voltage applied to bulk nodes of the transistors. The resistor(s) may maintain matching bias conditions for the transistors when they are turned off. In one exemplary design, one resistor may be coupled between the source and drain of each transistor. In another exemplary design, one resistor may be coupled between each intermediate node and the first voltage. The resistor(s) may maintain the source of each transistor at the first voltage.

Abstract: A phase locked loop (PLL) device is configurable in an analog phase locked loop and a hybrid analog-digital phase locked loop. In an analog mode, at least a phase detector, an analog loop filter, and a voltage controlled oscillator (VCO), are connected to form an analog loop. In a digital mode, at least the phase detector, the voltage controlled oscillator (VCO), a time to digital converter (TDC), a digital loop filter and a digital to analog converter (DAC) are connected to form the hybrid digital-analog loop.

Abstract: An FM radio with a wide frequency range operates in a cell phone without interfering with the VCO of the RF transceiver. The FM transceiver generates a VCO signal whose frequency varies by less than ±7% from the midpoint of a narrow first range. A synthesizer signal is generated by dividing the VCO frequency by a first divisor such that the synthesizer frequency varies over a lower frequency second range. The VCO frequency is also divided by a second divisor such that the synthesizer frequency varies over a third range. The upper limit of the second range falls at the lower limit of the third range. The lower limit of the second range is 85.5 MHz and the upper limit of the third range is 108.0 MHz. By also using a third divisor, a synthesizer signal with a range of 76-108 MHz is generated from the narrow first frequency range.

Abstract: Exemplary embodiments are directed to energy storage device security. An energy storage device may include at least one energy storage cell and a controller. The controller may be configured to request device identification data from an electronic device coupled to the energy storage device and compare the device identification data to device identification data stored in the energy storage device. The controller may be further configured to enable energy to be conveyed from the at least one energy storage cell to the electronic device if the device identification matches the stored device identification data.

Abstract: In one embodiment, this disclosure describes a frequency synthesizer for use in a wireless communication device, or similar device that requires precision frequency synthesis but small amounts of noise. In particular, the frequency synthesizer may include a phase locked loop (PLL) and an integrated voltage controlled oscillator (VCO). The frequency synthesizer may implement one or more calibration techniques to quickly and precisely calibrate the VCO. In this manner, the analog gain of the VCO can be significantly reduced, which may improve performance of the wireless communication device. Also, the initial state of the PLL may be improved to reduce lock time of the PLL, which may enhance performance of the wireless communication device.

Abstract: A phase locked loop (PLL) device is configurable in an analog phase locked loop and a hybrid analog-digital phase locked loop. In an analog mode, at least a phase detector, an analog loop filter, and a voltage controlled oscillator (VCO), are connected to form an analog loop. In a digital mode, at least the phase detector, the voltage controlled oscillator (VCO), a time to digital converter (TDC), a digital loop filter and a digital to analog converter (DAC) are connected to form the hybrid digital-analog loop.

Abstract: A phase locked loop (PLL) device includes a digital differentiator configured to differentiate a digital loop signal to at least partially compensate for the integration of an analog current signal by an analog integrator. A digital to analog converter (DAC) includes a current source output stage that generates the analog current signal based on an digital input signal. The analog integrator integrates the analog current signal to generate a voltage control signal for controlling a voltage controlled oscillator (VCO).

Abstract: Exemplary embodiments are directed to selective wireless power transfer. A method may include transferring wireless power to at least one electronic device while varying at least one parameter of the wireless power transfer according to a wireless power transfer scenario.

Abstract: Switches with connected bulk for improved switching performance and bias resistors for even voltage distribution to improve reliability are described. In an exemplary design, a switch may include a plurality of transistors coupled in a stack and at least one resistor coupled to at least one intermediate node in the stack. The transistors may have (i) a first voltage applied to a first transistor in the stack and (ii) a second voltage that is lower than the first voltage applied to bulk nodes of the transistors. The resistor(s) may maintain matching bias conditions for the transistors when they are turned off. In one exemplary design, one resistor may be coupled between the source and drain of each transistor. In another exemplary design, one resistor may be coupled between each intermediate node and the first voltage. The resistor(s) may maintain the source of each transistor at the first voltage.

Abstract: Exemplary embodiments are directed to wireless power. A method may comprise receiving wireless power with a receiver and charging an accumulator with energy from the received wireless power. The method may further include conveying energy from the accumulator to an energy storage device upon a charging level of the accumulator reaching a threshold level.

Abstract: An FM radio with a wide frequency range operates in a cell phone without interfering with the VCO of the RF transceiver. The FM transceiver generates a VCO signal whose frequency varies by less than ±7% from the midpoint of a narrow first range. A synthesizer signal is generated by dividing the VCO frequency by a first divisor such that the synthesizer frequency varies over a lower frequency second range. The VCO frequency is also divided by a second divisor such that the synthesizer frequency varies over a third range. The upper limit of the second range falls at the lower limit of the third range. The lower limit of the second range is 85.5 MHz and the upper limit of the third range is 108.0 MHz. By also using a third divisor, a synthesizer signal with a range of 76-108 MHz is generated from the narrow first frequency range.