Abstract: An apparatus is disclosed for a multi-band millimeter-wave (mmW) antenna array and radio-frequency integrated circuit (RFIC) module. In an example aspect, the apparatus includes a multi-band mmW antenna array and RFIC module with a first antenna array, a second antenna array, and at least one radio-frequency front-end integrated circuit. The first antenna array includes at least two first antenna elements and is tuned to a first mmW frequency band. The second antenna array includes at least two second antenna elements and is tuned to a second mmW frequency band. The at least one radio-frequency front-end integrated circuit includes at least two first transceiver chains and at least two second transceiver chains. The at least two first transceiver chains are respectively coupled to the at least two first antenna elements, and the at least two second transceiver chains are respectively coupled to the at least two second antenna elements.

Abstract: The present disclosure provides an amplifier circuit that includes one or more amplifier stages, each of the one or more amplifier stages including a complementary transistor configuration. The complementary transistor configuration includes an NMOS transistor and a PMOS transistor. The NMOS transistor is electrically coupled in parallel to the PMOS transistor. The amplifier circuit further includes an output amplifier stage electrically coupled to an output of the one or more amplifier stages, the output amplifier stage including a non-complementary transistor configuration including one or more NMOS transistors or PMOS transistors.

Abstract: A signal processing circuit reduces die size and power consumption for each antenna element. The signal processing circuit includes a first set of ports, a third port, a first path, a second path and a first transistor. The first path is between a first port of the first set of ports and the third port. The second path is between a second port of the first set of ports and the third port. The first transistor is coupled between the first path and the second path. The first transistor is configured to receive a control signal to control the first transistor to adjust an impedance between the first path and the second path.

Abstract: An apparatus is disclosed for bi-directional active phase shifting. In an example aspect, the apparatus includes a wireless transceiver. The wireless transceiver includes at least one transmit path and at least one receive path. The wireless transceiver also includes at least one active phase shifter disposed in both the transmit path and the receive path.

Abstract: A radio frequency (RF) architecture performs simultaneous beamforming to two different gigabit node Bs (gNBs) using an independent set of phase shifters. The beamforming process includes simultaneously communicating across a shared antenna aperture in a first frequency and a second frequency. The beamforming process also includes configuring a first beam for the first frequency and a second beam for the second frequency before communicating with the first frequency and/or the second frequency to synchronize communication between the first frequency and the second frequency across the shared antenna aperture.

Abstract: In conventional packaging strategies for mm wave applications, the size of the package is dictated by the antenna size, which is often much larger than the RFIC (radio frequency integrated circuit). Also, the operations are often limited to a single frequency which limits their utility. In addition, multiple addition build-up layers are required to provide the necessary separation between the antennas and ground layers. To address these issues, it is proposed to provide a device that includes an antenna package, an RFIC package, and an interconnect assembly between the antenna and the RFIC packages. The interconnect assembly may comprise a plurality of interconnects with high aspect ratios and configured to connect one or more antennas of the antenna package with an RFIC of the RFIC package. An air gap may be formed in between the antenna package and the RFIC package for performance improvement.

Abstract: A transmit/receive switching circuit implementation reduces transmitting/receiving switching losses in a transceiver during different modes of operation. The implementation includes connecting a low noise amplifier and a power amplifier in accordance with a shunt configuration in the transceiver. The implementation also includes disabling the power amplifier to achieve a high impedance state by grounding an output stage bias and enabling the low noise amplifier and disabling one or more transistors connected to a path between the low noise amplifier and the power amplifier during a receive mode.

Abstract: An apparatus is disclosed for a multi-band millimeter-wave (mmW) antenna array and radio-frequency integrated circuit (RFIC) module. In an example aspect, the apparatus includes a multi-band mmW antenna array and RFIC module with a first antenna array, a second antenna array, and at least one radio-frequency front-end integrated circuit. The first antenna array includes at least two first antenna elements and is tuned to a first mmW frequency band. The second antenna array includes at least two second antenna elements and is tuned to a second mmW frequency band. The at least one radio-frequency front-end integrated circuit includes at least two first transceiver chains and at least two second transceiver chains. The at least two first transceiver chains are respectively coupled to the at least two first antenna elements, and the at least two second transceiver chains are respectively coupled to the at least two second antenna elements.

Abstract: An apparatus is disclosed for bi-directional active phase shifting. In an example aspect, the apparatus includes a wireless transceiver. The wireless transceiver includes at least one transmit path and at least one receive path. The wireless transceiver also includes at least one active phase shifter disposed in both the transmit path and the receive path.

Abstract: A planar differential inductor reduces an effect of parasitics on common mode inductance of a voltage controlled oscillator (VCO)-based inductor to properly ground a common mode alternating current (AC) ground. In one instance, the planar differential inductor includes a ground plane, routing lines, distributed capacitors, an exterior inductor structure, and an interior inductor structure. The planar differential inductor may be coupled to a capacitor as part of an LC tank that operates as a resonator within a VCO. The bypass capacitor array is coupled between the ground plane and the routing lines. The exterior inductor structure is coupled between the routing lines and a power supply. The interior inductor is within the ground plane and coupled between the routing lines and differential ports.

Abstract: A radio frequency (RF) architecture performs simultaneous beamforming to two different gigabit node Bs (gNBs) using an independent set of phase shifters. The beamforming process includes simultaneously communicating across a shared antenna aperture in a first frequency and a second frequency. The beamforming process also includes configuring a first beam for the first frequency and a second beam for the second frequency before communicating with the first frequency and/or the second frequency to synchronize communication between the first frequency and the second frequency across the shared antenna aperture.

Abstract: The present disclosure provides an amplifier circuit that includes one or more amplifier stages, each of the one or more amplifier stages including a complementary transistor configuration. The complementary transistor configuration includes an NMOS transistor and a PMOS transistor. The NMOS transistor is electrically coupled in parallel to the PMOS transistor. The amplifier circuit further includes an output amplifier stage electrically coupled to an output of the one or more amplifier stages, the output amplifier stage including a non-complementary transistor configuration including one or more NMOS transistors or PMOS transistors.

Abstract: A signal processing circuit reduces die size and power consumption for each antenna element. The signal processing circuit includes a first set of ports, a third port, a first path, a second path and a first transistor. The first path is between a first port of the first set of ports and the third port. The second path is between a second port of the first set of ports and the third port. The first transistor is coupled between the first path and the second path. The first transistor is configured to receive a control signal to control the first transistor to adjust an impedance between the first path and the second path.

Abstract: A transmit/receive switching circuit implementation reduces transmitting/receiving switching losses in a transceiver during different modes of operation. The implementation includes connecting a low noise amplifier and a power amplifier in accordance with a shunt configuration in the transceiver. The implementation also includes disabling the power amplifier to achieve a high impedance state by grounding an output stage bias and enabling the low noise amplifier and disabling one or more transistors connected to a path between the low noise amplifier and the power amplifier during a receive mode.

Abstract: In conventional packaging strategies for mm wave applications, the size of the package is dictated by the antenna size, which is often much larger than the RFIC (radio frequency integrated circuit). Also, the operations are often limited to a single frequency which limits their utility. In addition, multiple addition build-up layers are required to provide the necessary separation between the antennas and ground layers. To address these issues, it is proposed to provide a device that includes an antenna package, an RFIC package, and an interconnect assembly between the antenna and the RFIC packages. The interconnect assembly may comprise a plurality of interconnects with high aspect ratios and configured to connect one or more antennas of the antenna package with an RFIC of the RFIC package. An air gap may be formed in between the antenna package and the RFIC package for performance improvement.

Abstract: A planar differential inductor reduces an effect of parasitics on common mode inductance of a voltage controlled oscillator (VCO)-based inductor to properly ground a common mode alternating current (AC) ground. In one instance, the planar differential inductor includes a ground plane, routing lines, distributed capacitors, an exterior inductor structure, and an interior inductor structure. The planar differential inductor may be coupled to a capacitor as part of an LC tank that operates as a resonator within a VCO. The bypass capacitor array is coupled between the ground plane and the routing lines. The exterior inductor structure is coupled between the routing lines and a power supply. The interior inductor is within the ground plane and coupled between the routing lines and differential ports.

Abstract: A radio frequency (RF) receiver device may include a receive path including a first amplifier. The device also includes a first mixer coupled to an output of the first amplifier and to an input of a second amplifier. Further, the device may include an auxiliary path including a second mixer coupled between an output of the first mixer and an input of the first mixer.

Abstract: A radio frequency (RF) receiver device may include a receive path including a first amplifier. The device also includes a first mixer coupled to an output of the first amplifier and to an input of a second amplifier. Further, the device may include an auxiliary path including a second mixer coupled between an output of the first mixer and an input of the first mixer.

Abstract: A frequency synthesizer within an FM receiver employs a Phase-Locked Loop (PLL) to generate a Local Oscillator (LO) signal. The LO signal is supplied to a mixer. The FM receiver also includes jammer detection functionality. If no jammer is detected, then the loop bandwidth of the PLL is set to have a relatively high value, thereby favoring suppression of in-band residual FM. If a jammer is detected, then the loop bandwidth of the PLL is set to have a relatively low value, thereby favoring suppression of out-of-band SSB phase noise. By adaptively changing loop bandwidth depending on whether a jammer is detected, performance requirements on sub-circuits within the PLL can be relaxed while still satisfying in-band residual FM and out-of-band SSB phase noise requirements. By allowing the VCO of the PLL to generate more phase noise due to the adaptive changing of loop bandwidth, VCO power consumption can be reduced.

Abstract: A frequency synthesizer within an FM receiver employs a Phase-Locked Loop (PLL) to generate a Local Oscillator (LO) signal. The LO signal is supplied to a mixer. The FM receiver also includes jammer detection functionality. If no jammer is detected, then the loop bandwidth of the PLL is set to have a relatively high value, thereby favoring suppression of in-band residual FM. If a jammer is detected, then the loop bandwidth of the PLL is set to have a relatively low value, thereby favoring suppression of out-of-band SSB phase noise. By adaptively changing loop bandwidth depending on whether a jammer is detected, performance requirements on sub-circuits within the PLL can be relaxed while still satisfying in-band residual FM and out-of-band SSB phase noise requirements. By allowing the VCO of the PLL to generate more phase noise due to the adaptive changing of loop bandwidth, VCO power consumption can be reduced.