Abstract: A regulator circuit and a method for compensating for sag in the output signal of the regulator circuit. A first comparator is coupled to an input of an oscillator, which oscillator outputs a clock signal and a ramp signal. In accordance with a feedback signal from the output of the regulator circuit, the clock and ramp signals of the oscillator are reset if the output signal sags to an undesirable level. The clock and ramp signals can be reset between active edges of the clock. The reset clock and ramp signals cause the regulator circuit to increase its output voltage to reduce the sag.

Abstract: In one embodiment, a PWM power supply controller asserts a PWM control signal synchronously to a clock signal of the PWM controller and also asserts the PWM control signal asynchronously to the clock signal.

Abstract: In one embodiment, an over-voltage protection circuit of a power supply system disables an upper power transistor of an output stage of the power supply system responsively to an over-voltage condition on an output voltage of the power supply system. Subsequently, the over-voltage protection circuit alternately enables and disables a lower power transistor of the output stage responsively to respective first and second value of the output voltage.